公开(公告)号：WO1998000916A1

公开(公告)日：1998-01-08

申请号：PCT/GB1997001611

申请日：1997-06-16

Applicant: SYMBIOS LOGIC INC. ,  GILL, David, Alan

Inventor： SYMBIOS LOGIC INC. ,  GILL, David, Alan ,  NGUYEN, Hoang ,  SCHULTZ, Richard, T.

IPC: H03K03/037

CPC classification number: H03K3/0375

Abstract: The invention provides for a meta-hardened circuit (100) that reduces the effects of metastability and includes a pulse generator (110) coupled to receive a first clock signal and generate in response thereto a second clock signal and an enable signal. A buffer (140), preferably tri-state, is coupled to receive a first data signal and the enable signal and generate in response thereto a second data signal. A bi-stable device (160), such as a flip-flop, is coupled to receive the second clock signal and the second data signal. The pulse generator (110) preferably includes a combining device (120) and a delay device (112). The buffer (140) preferably includes at least one tri-state inverter (144) and a keeper circuit (145). A method to reduce the metastability effects is also provided and includes the step of generating a delay between a second data input signal and a second clock signal that is greater than a delay between a first data input signal and a first clock signal. The step of generating preferably occurs in one clock cycle. The method also preferably includes generating an enable pulse by generating a second clock signal in response to a first clock signal and combining the first and second clock signals to generate the enable signal, and generating a second data input signal in response to a first data input signal, where generating the second data input signal includes receiving an enable signal. The method preferably includes the step of generating an output signal in response to the second data input signal and the second clock signal, the output signal having a reduced metastable effect.

Abstract translation: 本发明提供了减少亚稳态影响的元硬化电路（100），并且包括被连接以接收第一时钟信号并响应于此产生第二时钟信号和使能信号的脉冲发生器（110）。 耦合优选三态的缓冲器（140），以接收第一数据信号和使能信号，并响应于此产生第二数据信号。 诸如触发器的双稳态器件（160）被耦合以接收第二时钟信号和第二数据信号。 脉冲发生器（110）优选地包括组合装置（120）和延迟装置（112）。 缓冲器（140）优选地包括至少一个三态反相器（144）和保持器电路（145）。 还提供了一种降低亚稳效应的方法，包括产生第二数据输入信号和第二时钟信号之间的延迟的步骤，该延迟大于第一数据输入信号和第一时钟信号之间的延迟。 优选的发生步骤在一个时钟周期内发生。 该方法还优选地包括通过响应于第一时钟信号产生第二时钟信号并组合第一和第二时钟信号以产生使能信号来产生使能脉冲，以及响应于第一数据输入产生第二数据输入信号 信号，其中产生所述第二数据输入信号包括接收使能信号。 该方法优选地包括响应于第二数据输入信号和第二时钟信号产生输出信号的步骤，输出信号具有降低的亚稳效应。

公开(公告)号：WO1998000911A1

公开(公告)日：1998-01-08

申请号：PCT/GB1997001754

申请日：1997-06-26

Applicant: SYMBIOS LOGIC INC. ,  GILL, David, Alan

Inventor： SYMBIOS LOGIC INC. ,  GILL, David, Alan ,  GASPARIK, Frank

IPC: H03F03/45

CPC classification number: H03F3/4521 ,  H03F3/3028 ,  H03F2203/45508 ,  H03F2203/45656 ,  H03F2203/45658

Abstract: The invention provides for a receiver, such as a differential receiver (300), that includes a first input (302), a second input (304), and an output (306). The receiver (300) has a first signal path from the first input (302) to the output, the first signal path including a first differential amplifier (308) and a first active load (312) wherein the first differential amplifier (308) has an end connected to a first power supply voltage (VDD) and a second end connected to a second power supply voltage and the first active load (312). The first differential amplifier (308) also has a connection to the first input (302) and the second input (304), and the first active load (312) has a connection to the output (306). The receiver (300) also has a second signal path from the second input (304) to the output (306), the second signal path including a second differential amplifier (310) and second active load (314), wherein the second differential amplifier (310) has an end connected to a first power supply voltage and a second end connected to a second power supply voltage (VDD) and the second active load (314). The second differential amplifier (310) also has a connection to the first input (300) and the second input (304), and the second active load (314) has a connection to the output (306). The first signal path and the second signal path both have the same number of devices.

Abstract translation: 本发明提供了一种包括第一输入（302），第二输入（304）和输出（306）的接收器，例如差分接收器（300）。 接收器（300）具有从第一输入（302）到输出的第一信号路径，第一信号路径包括第一差分放大器（308）和第一有效负载（312），其中第一差分放大器（308）具有 连接到第一电源电压（VDD）的端部和连接到第二电源电压的第二端和第一有效负载（312）。 第一差分放大器（308）还具有与第一输入（302）和第二输入（304）的连接，并且第一有效负载（312）具有到输出（306）的连接。 接收机（300）还具有从第二输入（304）到输出（306）的第二信号路径，第二信号路径包括第二差分放大器（310）和第二有源负载（314），其中第二差分放大器 （310）具有连接到第一电源电压的端部和连接到第二电源电压（VDD）和第二有源负载（314）的第二端。 第二差分放大器（310）还具有与第一输入（300）和第二输入（304）的连接，并且第二有效负载（314）具有到输出端（306）的连接。 第一信号路径和第二信号路径都具有相同数量的设备。

公开(公告)号：WO1997050026A1

公开(公告)日：1997-12-31

申请号：PCT/GB1997001687

申请日：1997-06-23

Applicant: SYMBIOS LOGIC INC. ,  GILL, David, Alan

Inventor： SYMBIOS LOGIC INC. ,  GILL, David, Alan ,  GASPARIK, Frank

IPC: G05F03/26

CPC classification number: G05F3/267

Abstract: The invention provides for a bias current generator (10) which includes a first circuit component (MP2) having a first voltage developed across a pair of terminals thereof, the first voltage decreasing as an operating temperature of the first circuit component increases. The bias current generator further includes a second circuit component (Q2) having a second voltage developed across a pair of terminals thereof, the second voltage decreasing as an operating temperature of the second circuit component increases. In addition, the bias current generator (10) includes an impedance element (R2) connected to the first circuit component (MP2) and the second component (Q2), the impedance element (R2) having (i) an impedance which increases as an operating temperature of the impedance element increases, and (ii) a first current flowing therethrough, wherein a decrease in the first voltage causes a corresponding increase in the first current, and a decrease in the second voltage causes a corresponding increase in the first current. Moreover, the bias current generator (10) includes a mirroring circuit (MP3, MP4) for generating a second current which mirrors the first current flowing through the impedance element (R2). A method for generating a bias current that counteracts the effects temperature has upon electron and hole mobility is also disclosed.

Abstract translation: 本发明提供一种偏置电流发生器（10），该偏置电流发生器（10）包括第一电路部件（MP2），该第一电路部件具有在其一对端子上产生的第一电压，第一电压随第一电路部件的工作温度而降低。 偏置电流发生器还包括具有在其一对端子上产生的第二电压的第二电路部件（Q2），当第二电路部件的工作温度升高时，第二电压降低。 此外，偏置电流发生器（10）包括连接到第一电路部件（MP2）和第二部件（Q2）的阻抗元件（R2），阻抗元件（R2）具有（i） 阻抗元件的工作温度上升，并且（ii）流过其中的第一电流，其中第一电压的降低导致第一电流的相应增加，并且第二电压的降低导致第一电流的相应增加。 此外，偏置电流发生器（10）包括用于产生第二电流的镜像电路（MP3，MP4），其反射流过阻抗元件（R2）的第一电流。 还公开了一种用于产生抵消效应温度的偏置电流对电子和空穴迁移率的方法。

公开(公告)号：WO9707455A3

公开(公告)日：1997-03-20

申请号：PCT/GB9601837

申请日：1996-07-30

Applicant: SYMBIOS LOGIC INC ,  GILL DAVID ALAN

Inventor： DULAC KEITH BERNARD ,  PHILLIPS GROVER GEORGE

IPC: G06F3/06 ,  G06F11/10 ,  G06F11/20 ,  G06F13/00 ,  G11B20/10 ,  G11B31/00 ,  H04N5/765 ,  H04N7/173 ,  G06F11/00

CPC classification number: G06F11/201 ,  G06F11/1076 ,  G06F2201/85 ,  G06F2211/1014 ,  H04N7/17336

Abstract: The invention provides for a data storage apparatus including a first bus (104), a second bus (106), and a storage module (102) having a first and second output with the first output being connected to the first bus (104) and a second output being connected to the second bus (106). A first buffer storage (108) is connected to the first bus (104), and a second buffer storage (110) is connected to the second bus (106). The second buffer storage (110) includes an error correction module (110c), and first and second network adapters (112, 114) are connected to the first (104) and second (106) buses, respectively. The first network adapter (112) also includes a connection to the first buffer (108). A processor (120) in the apparatus includes a first processor means for transferring the data using a first path through the first output in the storage module (102) to the first buffer storage (108) and from the first buffer storage (108) to the first network adapter (112). A second processor means (120) is provided for transferring data using a second path through the second output to the second buffer storage (110) through the error correction module (110c) and from the second buffer storage (110) to the second network adapter (114), wherein the second processor means is responsive to an error in the storage module (102).

公开(公告)号：WO9807112A3

公开(公告)日：1998-04-23

申请号：PCT/GB9702147

申请日：1997-08-08

Applicant: SYMBIOS LOGIC INC ,  GILL DAVID ALAN

Inventor： BALLARE DANIEL E

IPC: G06F3/033 ,  G06F3/048 ,  G06K11/06

CPC classification number: G06F3/0488 ,  G06F3/04883 ,  G06F2203/04808

Abstract: The invention provides for a system for emulating a mouse button event via an absolute coordinate input device and which includes a computer having an operating system capable for receiving mouse type relative coordinate input commands from an absolute coordinte input device adapted to generate coordinate data in response to a finger touch down event. A controller is operably connected to the coordinate input device and adapted to resolve left and right mouse button touch down events and respective coordinate data for such events.

Abstract translation: 用于通过绝对坐标输入装置模拟鼠标按钮事件的系统。 该系统包括具有操作系统的计算机，该操作系统能够从适于响应于手指触碰事件产生坐标数据的绝对坐标输入装置接收鼠标类型的相对坐标输入命令。 控制器可操作地连接到坐标输入设备，并且适于解决左右鼠标按钮触摸事件和用于这种事件的相应坐标数据。

公开(公告)号：WO1998007112A2

公开(公告)日：1998-02-19

申请号：PCT/GB1997002147

申请日：1997-08-08

Applicant: SYMBIOS LOGIC INC. ,  GILL, David, Alan

Inventor： SYMBIOS LOGIC INC. ,  GILL, David, Alan ,  BALLARE, Daniel, E.

IPC: G06K11/06

CPC classification number: G06F3/0488 ,  G06F3/04883 ,  G06F2203/04808

Abstract: The invention provides for a system for emulating a mouse button event via an absolute coordinate input device and which includes a computer having an operating system capable for receiving mouse type relative coordinate input commands from an absolute coordinte input device adapted to generate coordinate data in response to a finger touch down event. A controller is operably connected to the coordinate input device and adapted to resolve left and right mouse button touch down events and respective coordinate data for such events.

Abstract translation: 本发明提供一种用于经由绝对坐标输入装置模拟鼠标按钮事件的系统，该系统包括具有操作系统的计算机，该操作系统能够从适于生成坐标数据的绝对协调输入装置接收鼠标型相对坐标输入命令， 手指触碰事件。 控制器可操作地连接到坐标输入设备并且适于解决左右鼠标按钮触摸事件和用于这种事件的相应坐标数据。

公开(公告)号：WO1998000917A1

公开(公告)日：1998-01-08

申请号：PCT/GB1997001688

申请日：1997-06-23

Applicant: SYMBIOS LOGIC INC. ,  GILL, David, Alan

Inventor： SYMBIOS LOGIC INC. ,  GILL, David, Alan ,  ANDERSON, Michael, B. ,  TABOR, Gregory, A. ,  JANDER, Mark, J.

IPC: H03K05/13

CPC classification number: H03L7/0805 ,  H03K3/0315 ,  H03K5/133 ,  H03L7/0995

Abstract: The invention provides for a precise timing delay method and apparatus in which a phase-locked loop (PLL) in combination with a timing reference is used to calibrate a precise delay. The delays are then duplicated throughout the chip and controlled by the same current as in the PLL. This makes the delay process, voltage, and temperature insensitive and the delays can be programmed by selecting the desired delay through a multiplexer. A high precision delay can be provided which is particularly advantageous for use in devices such as computer bus isolators.

Abstract translation: 本发明提供了精确的定时延迟方法和装置，其中使用与定时参考相结合的锁相环（PLL）来校准精确的延迟。 然后，这些延迟在整个芯片上复制并由与PLL中相同的电流控制。 这使得延迟过程，电压和温度不敏感，并且可以通过通过多路复用器选择所需的延迟来编程延迟。 可以提供高精度的延迟，这对于在例如计算机总线隔离器的设备中是特别有利的。

公开(公告)号：WO1998000845A1

公开(公告)日：1998-01-08

申请号：PCT/GB1997001744

申请日：1997-06-27

Applicant: SYMBIOS LOGIC INC. ,  GILL, David, Alan

Inventor： SYMBIOS LOGIC INC. ,  GILL, David, Alan ,  KYLE, Michael, G.

IPC: G11B20/10

CPC classification number: G11B20/10 ,  G11B19/02 ,  G11B19/12 ,  G11B27/105 ,  G11B27/3063 ,  G11B27/36 ,  G11B2220/213 ,  G11B2220/2545

Abstract: The present invention provides for a method of providing data to a memory device to be read at a first frequency comprising the steps of writing data to a memory device at a second frequency; blocking the writing of data after a predetermined amount of data is written; and writing data to the memory device in response to an address. Also included is a monitor circuit (70) comprising a monitor state machine (200) coupled to receive inputs including a comparison result, count signals and a load enable, and configured to output a data enable signal in response to the inputs.

Abstract translation: 本发明提供一种向第一频率读出的存储器件提供数据的方法，包括以第二频率将数据写入存储器件的步骤; 在写入预定量的数据之后阻止写入数据; 以及响应于地址将数据写入存储器件。 还包括监视器电路（70），监视器电路（70）包括监视状态机（200），其耦合以接收包括比较结果，计数信号和负载使能的输入，并且被配置为响应于输入而输出数据使能信号。

公开(公告)号：WO1997049031A1

公开(公告)日：1997-12-24

申请号：PCT/GB1997001655

申请日：1997-06-18

Applicant: SYMBIOS LOGIC INC. ,  GILL, David, Alan

Inventor： SYMBIOS LOGIC INC. ,  GILL, David, Alan ,  BORN, Richard, M.

IPC: G06F11/10

CPC classification number: G06F11/1076 ,  G06F11/10 ,  G06F11/2215 ,  G06F2211/1059 ,  G11B20/1833

Abstract: The invention provides for a distributed XOR device (120) that preferably includes a data buffer (140) which preferably stores at least two data blocks in an interleaved manner. The data blocks contains data words, and a specific data word for each data block contains CRC bits. In response to certain addresses, the data words of the data blocks are output from the data buffer (140) in an interleaved manner. An XOR engine circuit (170) receives the interleaved data words and preferably includes a data XOR circuit (200) and an error detection circuit (220). The data XOR circuit (200) preferably performs an exclusive-OR function on pairs of data words, where one data word is from a one data block and the other data word in from the other data block. The generated combinations or results are output to the error detection circuit (220). The error detection circuit (220) generates CRC bits from the generated combinations or results. Preferably, the CRC bits are encoded with a constant IDCRC. These encoded CRC bits are compared to the result of the exclusive-OR function on the CRC bits of the data blocks. If these bits are not equal, an error signal is output. The comparison therefore checks whether the XOR engine circuit (170) or the data blocks are in error.

Abstract translation: 本发明提供了一种优选地包括数据缓冲器（140）的分布式异或装置（120），其优选地以交错方式存储至少两个数据块。 数据块包含数据字，每个数据块的特定数据字包含CRC位。 响应于某些地址，数据块的数据字以交错方式从数据缓冲器（140）输出。 XOR引擎电路（170）接收交织的数据字，并且优选地包括数据XOR电路（200）和错误检测电路（220）。 数据XOR电路（200）优选地对数据字对执行异或运算，其中一个数据字来自一个数据块，另一个数据字来自另一个数据块。 所生成的组合或结果被输出到错误检测电路（220）。 误差检测电路（220）根据所生成的组合或结果生成CRC位。 优选地，CRC位用常数IDCRC编码。 这些编码的CRC位与数据块的CRC位的异或运算结果进行比较。 如果这些位不相等，则输出错误信号。 因此，比较检查XOR发动机电路（170）或数据块是否有错误。

公开(公告)号：WO1997037298A1

公开(公告)日：1997-10-09

申请号：PCT/GB1997000952

申请日：1997-03-26

Applicant: SYMBIOS LOGIC INC. ,  GILL, David, Alan

Inventor： SYMBIOS LOGIC INC. ,  GILL, David, Alan ,  KASYON, Jeffrey, D. ,  JANDER, Mark, J.

IPC: G06F05/06

CPC classification number: G06F5/06

Abstract: The invention provides for a first-in-first-out (FIFO) memory system having a first fall-through FIFO (102; 302) having an input and an output, a pointer-based FIFO having an input and an output, wherein the input of the pointer-based FIFO (104; 304) is connected to the output of the first fall-through FIFO, and a second fall-through FIFO (106; 306) having an input and an output, wherein the input of the second fall-through FIFO (106; 306) is connected to the output of the pointer-based FIFO (104; 304), wherein data placed into the input of the first fall-through FIFO (102; 302) appears at the output of the second fall-through FIFO (106; 306) in a first-in-first-out basis.

Abstract translation: 本发明提供了具有具有输入和输出的第一下降FIFO（102; 302）的先进先出（FIFO）存储器系统，具有输入和输出的基于指针的FIFO，其中， 基于指针的FIFO（104; 304）的输入连接到第一下降FIFO的输出端和具有输入和输出的第二下降FIFO（106; 306），其中第二 直通FIFO（106; 306）连接到基于指针的FIFO（104; 304）的输出，其中放置在第一下降FIFO（102; 302）的输入中的数据出现在 第二通过FIFO（106; 306）。