公开(公告)号：US09893692B2

公开(公告)日：2018-02-13

申请号：US15352877

申请日：2016-11-16

Applicant: Tensorcom, Inc.

Inventor： Zaw Soe ,  Kevin Jing ,  Steve Gao

IPC: H03G1/00 ,  H03F3/45 ,  H03G5/28

CPC classification number: H03G1/007 ,  H03F3/45197 ,  H03F2200/165 ,  H03F2200/69 ,  H03F2203/45372 ,  H03F2203/45374 ,  H03F2203/45512 ,  H03F2203/45544 ,  H03F2203/45594 ,  H03F2203/45686 ,  H03F2203/45702 ,  H03G5/28 ,  H03H11/1286

Abstract: A circuit comprises a Sallen-Key filter, which includes a source follower that implements a unity-gain amplifier; and a programmable-gain amplifier coupled to the Sallen-Key filter. The circuit enables programmable gain via adjustment to a current mirror copying ratio in the programmable-gain amplifier, which decouples the bandwidth of the circuit from its gain settings. The programmable-gain amplifier can comprise a differential voltage-to-current converter, a current mirror pair, and programmable output gain stages. The Sallen-Key filter and at least one branch in the programmable-gain amplifier can comprise transistors arranged in identical circuit configurations.

公开(公告)号：US20170317668A1

公开(公告)日：2017-11-02

申请号：US15652934

申请日：2017-07-18

Applicant: Tensorcom, Inc.

Inventor： Dai Dai

IPC: H03K5/24 ,  H03H11/48 ,  H03M1/00 ,  H03M1/18 ,  H03M1/08

CPC classification number: H03K5/2481 ,  H03H11/481 ,  H03M1/002 ,  H03M1/0836 ,  H03M1/0845 ,  H03M1/183

Abstract: A circuit comprises a first amplifier coupled to a first and a second node; a differential capacitive load coupled to the first and the second node, the differential capacitive load coupled between drains of transistors in a cross coupled transistor circuit; a current mirror coupled to a source of each transistor; and a capacitor coupled between the sources of the transistors. A plurality of amplifiers can be coupled to the differential capacitive load, wherein each amplifier comprises a clock-less pre-amplifier of a comparator. The amplifiers may be abutted to one another such that an active transistor of a first differential stage in a first amplifier behaves as a dummy transistor for an adjacent differential stage in a second amplifier

公开(公告)号：US20170272109A1

公开(公告)日：2017-09-21

申请号：US15505444

申请日：2015-08-25

Applicant: Tensorcom, Inc.

Inventor： KhongMeng Tham ,  Huainan Ma ,  Zaw Soe ,  Ricky Lap Kei Cheung

IPC: H04B1/04 ,  H03D7/12

CPC classification number: H04B1/0475 ,  H03C2200/0058 ,  H03D3/008 ,  H03D3/009 ,  H03D7/125 ,  H03D7/165 ,  H04B1/04 ,  H04B1/0458 ,  H04B2001/0408

Abstract: Local oscillator (LO) leakage and Image are common and undesirable effects in typical transmitters. Typically, fairly complex hardware and algorithms are used to calibrate and reduce these impairments. A single transistor that draws essentially no dc current and occupies a very small area detects the LO leakage and Image signals. The single transistor operating as a square-law device is used to mix the signals at the input and output ports of a power amplifier. The mixed signal generated by the single transistor enables the simultaneous calibration of the LO leakage and Image Rejection.

公开(公告)号：US20170063362A1

公开(公告)日：2017-03-02

申请号：US15340430

申请日：2016-11-01

Applicant: Tensorcom, Inc.

Inventor： Dai Dai

IPC: H03K5/24 ,  H03H11/48

CPC classification number: H03K5/2481 ,  H03H11/481 ,  H03M1/002 ,  H03M1/0836 ,  H03M1/0845 ,  H03M1/183

Abstract: A circuit comprises a first amplifier coupled to a first and a second node; a differential capacitive load coupled to the first and the second node, the differential capacitive load coupled between drains of transistors in a cross coupled transistor circuit; a current mirror coupled to a source of each transistor; and a capacitor coupled between the sources of the transistors. A plurality of amplifiers can be coupled to the differential capacitive load, wherein each amplifier comprises a clock-less pre-amplifier of a comparator. The amplifiers may be abutted to one another such that an active transistor of a first differential stage in a first amplifier behaves as a dummy transistor for an adjacent differential stage in a second amplifier

Abstract translation: 电路包括耦合到第一和第二节点的第一放大器; 耦合到第一和第二节点的差分电容性负载，耦合在交叉耦合晶体管电路中的晶体管的漏极之间的差分电容性负载; 耦合到每个晶体管的源极的电流镜; 以及耦合在晶体管的源极之间的电容器。 多个放大器可以耦合到差分电容性负载，其中每个放大器包括比较器的无时钟前置放大器。 放大器可以彼此邻接，使得第一放大器中的第一差分级的有源晶体管在第二放大器中用作相邻差分级的虚拟晶体管

公开(公告)号：US09276610B2

公开(公告)日：2016-03-01

申请号：US14165505

申请日：2014-01-27

Applicant: Tensorcom, Inc.

Inventor： Bo Xia ,  Ricky Lap Kei Cheung ,  Bo Lu

IPC: H03M13/11

CPC classification number: H03M13/1145 ,  H03M13/1122 ,  H03M13/114 ,  H03M13/1148 ,  H03M13/116

Abstract: The architecture is able to switch to Non-blocking check-node-update (CNU) scheduling architecture which has better performance than blocking CNU scheduling architecture. The architecture uses an Offset Min-Sum with Beta=1 with a clock domain operating at 440 MHz. The constraint macro-matrix is a spare matrix where each “1’ corresponds to a sub-array of a cyclically shifted identity matrix which is a shifted version of an identity matrix. Four core processors are used in the layered architecture where the constraint matrix uses a sub-array of 42 (check nodes)×42 (variable nodes) in the macro-array of 168×672 bits. Pipeline processing is used where the delay for each layer only requires 4 clock cycles.

Abstract translation: 该架构能够切换到具有比阻塞CNU调度架构更好的性能的非阻塞校验节点更新（CNU）调度体系结构。 该架构使用Beta = 1的偏移最小和，时钟域工作在440 MHz。 约束宏矩阵是备用矩阵，其中每个“1”对应于作为单位矩阵的移位版本的循环移位单位矩阵的子阵列。 在分层架构中使用四个核心处理器，约束矩阵在168×672位的宏阵列中使用42（校验节点）×42（变量节点）的子阵列。 使用管道处理，其中每层的延迟只需要4个时钟周期。

公开(公告)号：US09264056B2

公开(公告)日：2016-02-16

申请号：US14672214

申请日：2015-03-29

Applicant: Tensorcom, Inc.

Inventor： Dai Dai

IPC: H03M1/12 ,  H03M1/00 ,  H03K5/24 ,  H03M1/08 ,  H03M1/18 ,  H03H11/48

CPC classification number: H03K5/2481 ,  H03H11/481 ,  H03M1/002 ,  H03M1/0836 ,  H03M1/0845 ,  H03M1/183

Abstract: The differential output of a Programmable Gain Amplifier (PGA) is loaded by the input differential gate capacitance of a plurality of Analog to Digital convertors (ADC) comparators and the differential metal layer traces to interconnect these comparators to the PGA. The differential capacitive load presented to the PGA is quite large and reduces the bandwidth of this interconnect between the PGA and ADC. To overcome the performance degradation due to the differential capacitive load, an active negative-capacitor circuit cancels the effect of the large input capacitance of the ADC comparators. This cancelation extends the gain characteristics of the interconnect between the PGA's output and the inputs of the first stage of the comparators. The active negative-capacitance is comprised of a cross pair NMOS with a capacitor connecting their sources where each NMOS is biased by a current source.

Abstract translation: 可编程增益放大器（PGA）的差分输出由多个模数转换器（ADC）比较器的输入差分栅极电容和差分金属层迹线加载，以将这些比较器与PGA互连。 提供给PGA的差分电容性负载相当大，并降低了PGA和ADC之间的这种互连的带宽。 为了克服由于差分电容性负载引起的性能下降，有源负电容电路消除了ADC比较器的大输入电容的影响。 该取消扩展了PGA输出与比较器的第一级的输入之间的互连的增益特性。 有源负电容由交叉对NMOS组成，其中电容器连接其源极，其中每个NMOS由电流源偏置。

公开(公告)号：US20150214980A1

公开(公告)日：2015-07-30

申请号：US14165505

申请日：2014-01-27

Applicant: Tensorcom, Inc.

Inventor： Bo Xia ,  Ricky Lap Kei Cheung ,  Bo Lu

IPC: H03M13/11

CPC classification number: H03M13/1145 ,  H03M13/1122 ,  H03M13/114 ,  H03M13/1148 ,  H03M13/116

Abstract: The architecture is able to switch to Non-blocking check-node-update (CNU) scheduling architecture which has better performance than blocking CNU scheduling architecture. The architecture uses an Offset Min-Sum with Beta=1 with a clock domain operating at 440 MHz. The constraint macro-matrix is a spare matrix where each “1’ corresponds to a sub-array of a cyclically shifted identity matrix which is a shifted version of an identity matrix. Four core processors are used in the layered architecture where the constraint matrix uses a sub-array of 42 (check nodes)×42 (variable nodes) in the macro-array of 168×672 bits. Pipeline processing is used where the delay for each layer only requires 4 clock cycles.

Abstract translation: 该架构能够切换到具有比阻塞CNU调度架构更好的性能的非阻塞校验节点更新（CNU）调度体系结构。 该架构使用Beta = 1的偏移最小和，时钟域工作在440 MHz。 约束宏矩阵是备用矩阵，其中每个“1”对应于作为单位矩阵的移位版本的循环移位单位矩阵的子阵列。 在分层架构中使用四个核心处理器，约束矩阵在168×672位的宏阵列中使用42（校验节点）×42（变量节点）的子阵列。 使用管道处理，其中每层的延迟只需要4个时钟周期。

公开(公告)号：US08836407B1

公开(公告)日：2014-09-16

申请号：US13789681

申请日：2013-03-08

Applicant: Tensorcom, Inc.

Inventor： Zaw Soe ,  Tham KhongMeng

IPC: G06F7/44 ,  G06G7/16

CPC classification number: G06G7/16 ,  H03D7/1441 ,  H03D7/1458 ,  H03D7/165 ,  H03D2200/0019

Abstract: A cross coupled NMOS transistors providing a negative gm transistor feedback allows a mixer to saturate at a reduced input signal swing voltage when compared to a conventional mixer allowing the mixer to enter into the current mode operation at a reduced signal input voltage range. The linearity of the baseband signal path can be traded against the mixer gain and is improved if the signal swing in the baseband signal path is reduced. The input mixer transistors operate in the saturated mode at a reduced input signal swing voltage causing the power efficiency of the system to increase since the transmit chain operates at a class-D power efficient. Efficiency is very important in mobile applications to save and extend the battery power of a mobile phone providing a better utilization of the available power since most of that power is supplied to the energy of the outgoing modulated signal.

Abstract translation: 提供负gm晶体管反馈的交叉耦合NMOS晶体管使混频器能够与传统的混频器相比，作为降低的输入信号摆幅电压饱和，从而允许混频器在降低的信号输入电压范围内进入电流模式操作。 基带信号路径的线性度可以抵抗混频器增益进行交易，如果基带信号路径中的信号摆幅减小，则可以得到改善。 输入混频器晶体管以降低的输入信号摆幅电压在饱和模式下工作，导致系统的功率效率增加，因为发射链以D类功率有效工作。 在移动应用中，效率对于节省和扩展移动电话的电池电力是非常重要的，其提供了对可用功率的更好的利用，因为大部分功率被提供给输出调制信号的能量。

公开(公告)号：WO2017087485A1

公开(公告)日：2017-05-26

申请号：PCT/US2016/062224

申请日：2016-11-16

Applicant: TENSORCOM, INC.

Inventor： SOE, Zaw ,  JING, Kevin ,  GAO, Steve

IPC: H03G3/30 ,  H03F3/45 ,  H03H11/12

CPC classification number: H03G1/007 ,  H03F3/45197 ,  H03F2200/165 ,  H03F2200/69 ,  H03F2203/45372 ,  H03F2203/45374 ,  H03F2203/45512 ,  H03F2203/45544 ,  H03F2203/45594 ,  H03F2203/45686 ,  H03F2203/45702 ,  H03G5/28 ,  H03H11/1286

Abstract: A circuit comprises a Sallen-Key filter, which includes a source follower that implements a unity-gain amplifier; and a programmable-gain amplifier coupled to the Sallen-Key filter. The circuit enables programmable gain via adjustment to a current mirror copying ratio in the programmable-gain amplifier, which decouples the bandwidth of the circuit from its gain settings. The programmable-gain amplifier can comprise a differential voltage-to-current converter, a current mirror pair, and programmable output gain stages. The Sallen-Key filter and at least one branch in the programmable-gain amplifier can comprise transistors arranged in identical circuit configurations.

Abstract translation: 一种电路包括Sallen-Key滤波器，其包括实现单位增益放大器的源极跟随器; 和一个耦合到Sallen-Key滤波器的可编程增益放大器。 该电路通过调节可编程增益放大器中的电流镜像复制比来启用可编程增益，该放大器将电路的带宽与其增益设置分离。 可编程增益放大器可以包括差分电压 - 电流转换器，电流镜像对和可编程输出增益级。 Sallen-Key滤波器和可编程增益放大器中的至少一个分支可以包括以相同电路配置排列的晶体管。

公开(公告)号：WO2013173176A1

公开(公告)日：2013-11-21

申请号：PCT/US2013/040486

申请日：2013-05-10

Applicant: TENSORCOM, INC.

Inventor： DAI, dai

IPC: H03M1/66

CPC classification number: H03M1/06 ,  H03M1/765

Abstract: A critical design parameter occurs when digital signals are converted into analog signals. Generating a relative large swing with a resistor-ladder DAC becomes more difficult as the supply voltage drops to less than 2 times the threshold voltage. For a 5 bit DAC, 32 sub-arrays select the appropriate voltage from the series coupled resistor network. Each sub-array uses p-channel transistors where the sub-array extracting the lowest voltage 700mV only has a 100mV of gate to source voltage. To compensate for the reduced gate to source voltage, the sub-arrays are partitioned into four groups. In each group, the p-channel width is increased from 2um to 5um, as the tap voltage drops from 1.2 V to 0.7 V. This allows the p-channel transistor with a small gate to source voltage to have a larger width thereby improving performance.

Abstract translation: 当数字信号转换成模拟信号时，出现关键设计参数。 随着电源电压下降到阈值电压的2倍，电阻梯形DAC产生相对较大的摆幅变得更加困难。 对于5位DAC，32个子阵列从串联电阻网络中选择合适的电压。 每个子阵列使用p沟道晶体管，其中提取最低电压700mV的子阵列仅具有100mV的栅极至源极电压。 为了补偿栅极到源极电压的降低，子阵列被分成四组。 在每组中，随着分接电压从1.2V下降到0.7V，p沟道宽度从2um增加到5um。这允许具有较小栅极源极电压的p沟道晶体管具有较大的宽度，从而提高性能 。