公开(公告)号：EP3378159A1

公开(公告)日：2018-09-26

申请号：EP16867015.6

申请日：2016-11-16

Applicant: Tensorcom, Inc.

Inventor： SOE, Zaw ,  JING, Kevin ,  GAO, Steve

IPC: H03G3/30 ,  H03F3/45 ,  H03H11/12

CPC classification number: H03G1/007 ,  H03F3/45197 ,  H03F2200/165 ,  H03F2200/69 ,  H03F2203/45372 ,  H03F2203/45374 ,  H03F2203/45512 ,  H03F2203/45544 ,  H03F2203/45594 ,  H03F2203/45686 ,  H03F2203/45702 ,  H03G5/28 ,  H03H11/1286

Abstract: A circuit comprises a Sallen-Key filter, which includes a source follower that implements a unity-gain amplifier; and a programmable-gain amplifier coupled to the Sallen-Key filter. The circuit enables programmable gain via adjustment to a current mirror copying ratio in the programmable-gain amplifier, which decouples the bandwidth of the circuit from its gain settings. The programmable-gain amplifier can comprise a differential voltage-to-current converter, a current mirror pair, and programmable output gain stages. The Sallen-Key filter and at least one branch in the programmable-gain amplifier can comprise transistors arranged in identical circuit configurations.

公开(公告)号：WO2013085966A1

公开(公告)日：2013-06-13

申请号：PCT/US2012/067898

申请日：2012-12-05

Applicant: TENSORCOM, INC.

Inventor： SOE, Zaw

IPC: H04B1/16 ,  H03D7/00

CPC classification number: H03D7/1441 ,  H03D7/1466 ,  H03F1/223 ,  H03F3/193

Abstract: A cascode common source and common gate LNAs operating at 60GHz are introduced and described. The cascode common source LNA is simulated to arrive at an optimum ratio of upper device width to the lower device width. The voltage output of the cascode common source LNA is translated into a current to feed and apply energy to the mixer stage. These input current signals apply the energy associated with the current directly into the switched capacitors in the mixer to minimize the overall power dissipation of the system. The LNA is capacitively coupled to the mixer switches in the I and Q mixers and are enabled and disabled by the clocks generated by the quadrature oscillator. These signals are then amplified by a differential amplifier to generate the sum and difference frequency spectra.

Abstract translation: 引入并描述了以60GHz工作的共源共栅和公共栅极LNA。 对共源共栅源LNA进行模拟，以达到上部器件宽度与较低器件宽度的最佳比例。 共源共栅源LNA的电压输出转换为电流以馈送并将能量施加到混频器级。 这些输入电流信号将与电流相关联的能量直接施加到混频器中的开关电容器中，以最小化系统的总功耗。 LNA电容耦合到I和Q混频器中的混频器开关，并由正交振荡器产生的时钟使能和禁止。 然后，这些信号被差分放大器放大以产生和和差频谱。

公开(公告)号：WO2016033073A1

公开(公告)日：2016-03-03

申请号：PCT/US2015/046740

申请日：2015-08-25

Applicant: TENSORCOM, INC.

Inventor： THAM, KhongMeng ,  MA, Huainan ,  SOE, Zaw ,  CHEUNG, Ricky Lap Kei

IPC: H03D7/18 ,  H03D7/12 ,  H04B1/04

CPC classification number: H04B1/0475 ,  H03C2200/0058 ,  H03D3/008 ,  H03D3/009 ,  H03D7/125 ,  H03D7/165 ,  H04B1/04 ,  H04B1/0458 ,  H04B2001/0408

Abstract: Local oscillator (LO) leakage and Image are common and undesirable effects in typical transmitters. Typically, fairly complex hardware and algorithms are used to calibrate and reduce these impairments. A single transistor that draws essentially no dc current and occupies a very small area detects the LO leakage and Image signals. The single transistor operating as a square-law device is used to mix the signals at the input and output ports of a power amplifier. The mixed signal generated by the single transistor enables the simultaneous calibration of the LO leakage and Image Rejection.

Abstract translation: 本地振荡器（LO）泄漏和图像是典型发射器中常见的和不良影响。 通常，相当复杂的硬件和算法用于校准和减少这些损伤。 基本上没有直流电流并且占用非常小的区域的单个晶体管检测LO泄漏和图像信号。 作为平方律器件工作的单个晶体管用于混合功率放大器的输入和输出端口处的信号。 由单个晶体管产生的混合信号可以同时校准LO泄漏和图像抑制。

公开(公告)号：WO2013085971A1

公开(公告)日：2013-06-13

申请号：PCT/US2012/067908

申请日：2012-12-05

Applicant: TENSORCOM, INC.

Inventor： SOE, Zaw

IPC: H03B19/06 ,  H03L7/18

CPC classification number: H03D7/1441 ,  H03D7/1466 ,  H03F1/223 ,  H03F3/193

Abstract: Injection locked dividers provide a divided clock signal after being driven by a injected clock signal that is a multiple of the divided clock signal. At injected clock signal at 60 GHz generates a differential 30 GHz clock signal. One innovative construction of the injection locked oscillator reduces the internal capacitive at a node by associating the parasitic capacitance at this node with the inductors of the tapped inductor resonant circuit. This provides more energy flow in the injection pulses applied to the legs of the injection locked circuit providing an increase locking range.

Abstract translation: 注入锁定分频器在被分配的时钟信号的倍数的注入时钟信号驱动之后提供分频时钟信号。 在60 GHz的注入时钟信号产生差分30 GHz时钟信号。 注入锁定振荡器的一个创新结构通过将该节点处的寄生电容与抽头电感谐振电路的电感相关联来减少节点处的内部电容。 这提供了施加到注射锁定电路的腿部的注射脉冲中提供更多的能量流，从而提供增加的锁定范围。

公开(公告)号：WO2017087485A1

公开(公告)日：2017-05-26

申请号：PCT/US2016/062224

申请日：2016-11-16

Applicant: TENSORCOM, INC.

Inventor： SOE, Zaw ,  JING, Kevin ,  GAO, Steve

IPC: H03G3/30 ,  H03F3/45 ,  H03H11/12

CPC classification number: H03G1/007 ,  H03F3/45197 ,  H03F2200/165 ,  H03F2200/69 ,  H03F2203/45372 ,  H03F2203/45374 ,  H03F2203/45512 ,  H03F2203/45544 ,  H03F2203/45594 ,  H03F2203/45686 ,  H03F2203/45702 ,  H03G5/28 ,  H03H11/1286

Abstract: A circuit comprises a Sallen-Key filter, which includes a source follower that implements a unity-gain amplifier; and a programmable-gain amplifier coupled to the Sallen-Key filter. The circuit enables programmable gain via adjustment to a current mirror copying ratio in the programmable-gain amplifier, which decouples the bandwidth of the circuit from its gain settings. The programmable-gain amplifier can comprise a differential voltage-to-current converter, a current mirror pair, and programmable output gain stages. The Sallen-Key filter and at least one branch in the programmable-gain amplifier can comprise transistors arranged in identical circuit configurations.

Abstract translation: 一种电路包括Sallen-Key滤波器，其包括实现单位增益放大器的源极跟随器; 和一个耦合到Sallen-Key滤波器的可编程增益放大器。 该电路通过调节可编程增益放大器中的电流镜像复制比来启用可编程增益，该放大器将电路的带宽与其增益设置分离。 可编程增益放大器可以包括差分电压 - 电流转换器，电流镜像对和可编程输出增益级。 Sallen-Key滤波器和可编程增益放大器中的至少一个分支可以包括以相同电路配置排列的晶体管。

公开(公告)号：WO2013043957A2

公开(公告)日：2013-03-28

申请号：PCT/US2012/056466

申请日：2012-09-21

Applicant: TENSORCOM, INC.

Inventor： SOE, Zaw

IPC: H03B1/00 ,  H03F3/45

CPC classification number: H03F3/45179 ,  H03F3/45475 ,  H03F3/505 ,  H03F2203/45138 ,  H03F2203/45394 ,  H03H11/1213 ,  H03H11/1286

Abstract: Very high frequency circuits suffer from parasitic resistances. At 60 GHz, conventional layout techniques can introduce loss into the circuit at critical locations. One critical interconnect between the output of a pre-driver and the gate of the final output stage causes 1 or 2 dB of loss due to the layout. By minimizing the number of via contacts, this conventional loss can be recovered using this new layout technique. In addition, a tap point of a via stack is used to modify the resonant characteristics of the interconnect. Finally, cross coupled devices in a resonant circuit are used to reduce the common mode noise at the expense of the common mode gain.

Abstract translation: 超高频电路遭受寄生电阻。 在60GHz，传统的布局技术可以在关键位置引入电路损耗。 预驱动器的输出和最终输出级的栅极之间的一个关键互连会导致由于布局导致1或2 dB的损耗。 通过最小化通孔触点的数量，可以使用这种新的布局技术来恢复传统的损耗。 此外，使用通孔堆叠的抽头点来修改互连的谐振特性。 最后，谐振电路中的交叉耦合器件用于以共模增益为代价来降低共模噪声。

公开(公告)号：WO2013043954A2

公开(公告)日：2013-03-28

申请号：PCT/US2012/056463

申请日：2012-09-21

Applicant: TENSORCOM, INC.

Inventor： SOE, Zaw

IPC: H03B1/00 ,  H03F3/45

CPC classification number: H03F3/45179 ,  H03F3/45475 ,  H03F3/505 ,  H03F2203/45138 ,  H03F2203/45394 ,  H03H11/1213 ,  H03H11/1286

Abstract: A phase lock loop (PLL) is an important component in wireless systems. CMOS technology offers voltage controlled oscillator designs operating at 60 GHz. One of the difficulties is dividing the high frequency clock down to a manageable clock frequency using conventional CMOS. Although injection locked dividers can divide down this clock frequency, these dividers have limitations. A divide by 2 is presented that uses several techniques; feed forward, clock amplification and series peaked inductors to overcome these limitations.

Abstract translation: 锁相环（PLL）是无线系统中的重要组成部分。 CMOS技术提供工作在60 GHz的压控振荡器设计。 其中一个难题是使用传统CMOS将高频时钟分频为可管理的时钟频率。 虽然注入锁定分频器可以分解这个时钟频率，但这些分频器有局限性。 除以2表示使用几种技术; 前馈，时钟放大和串联峰值电感来克服这些限制。

公开(公告)号：WO2013043950A1

公开(公告)日：2013-03-28

申请号：PCT/US2012/056458

申请日：2012-09-21

Applicant: TENSORCOM, INC.

Inventor： SOE, Zaw

IPC: H03F3/45

CPC classification number: H03F3/45179 ,  H03F3/45475 ,  H03F3/505 ,  H03F2203/45138 ,  H03F2203/45394 ,  H03H11/1213 ,  H03H11/1286

Abstract: A Sallen-Key filter requires an operational amplifier with a large input impedance and a small output impedance. The operational amplifier requires an internal feedback path for stability that limits performance. This invention eliminates the need for internal feedback and increases the gain of a source follower which has characteristics matching the operational amplifier in the Sallen-Key filter. The source follower provides 6dB of AC voltage gain and is substituted for the operational amplifier. The Sallen-Key filter requires a differential configuration to generate all the required signals with their compliments and uses these signals in a feed forward path. Furthermore, a two n-channel stacked device maximizes the headroom voltage to several hundred millivolts for a 1.2V voltage supply in a 40nm CMOS technology. Thus, the required 880MHz bandwidth of the Sallen-Key filter can be easily met using the innovative source follower.

Abstract translation: Sallen-Key滤波器需要具有大输入阻抗和小输出阻抗的运算放大器。 运算放大器需要一个内部反馈路径来稳定性，从而限制性能。 本发明消除了对内部反馈的需要，并且增加了具有与Sallen-Key滤波器中的运算放大器匹配的特性的源极跟随器的增益。 源极跟随器提供6dB的交流电压增益，代替运算放​​大器。 Sallen-Key滤波器需要差分配置，以产生所有需要的信号，并在前馈路径中使用这些信号。 此外，在40nm CMOS技术中，两个n沟道堆叠器件可以将裕量电压最大化为数百毫伏，用于1.2V电压源。 因此，使用创新的源跟随器可以轻松满足Sallen-Key滤波器所需的880MHz带宽。

公开(公告)号：WO2012174497A1

公开(公告)日：2012-12-20

申请号：PCT/US2012/042837

申请日：2012-06-16

Applicant: TENSORCOM INC. ,  THAM, KhongMeng ,  SOE, Zaw

Inventor： THAM, KhongMeng ,  SOE, Zaw

IPC: H04B7/00

CPC classification number: H03K3/012 ,  G05F3/16 ,  H01Q1/50 ,  H03K17/56 ,  H04B5/0075

Abstract: This invention eliminates the need for "capacitor coupling" or "transformer coupling," and the associated undesirable parasitic capacitance and inductance associated with these coupling techniques when designing high frequency (~60GHz) circuits. At this frequency, the distance between two adjacent stages needs to be minimized. A resonant circuit in series with the power or ground leads is used to isolate a biasing signal from a high frequency signal. The introduction of this resonant circuit allows a first stage to be "directly coupled" to a next stage using a metallic trace. The "direct coupling" technique passes both the high frequency signal and the biasing voltage to the next stage. The "direct coupling" approach overcomes the large die area usage when compared to either the "AC coupling" or "transformer coupling" approach since neither capacitors nor transformers are required to transfer the high frequency signals between stages.

Abstract translation: 当设计高频（〜60GHz）电路时，本发明消除了对“电容器耦合”或“变压器耦合”的需要以及与这些耦合技术相关联的不期望的寄生电容和电感。 在这个频率下，两个相邻阶段之间的距离需要最小化。 与电源或接地引线串联的谐振电路用于将偏置信号与高频信号隔离开来。 该谐振电路的引入允许使用金属迹线将第一级“直接耦合”到下一级。 “直接耦合”技术将高频信号和偏置电压都通过下一级。 与“AC耦合”或“变压器耦合”方法相比，“直接耦合”方法克服了大的管芯面积使用，因为既不需要电容器也不需要变压器来在级之间传输高频信号。