公开(公告)号：WO1991003875A1

公开(公告)日：1991-03-21

申请号：PCT/US1990004845

申请日：1990-08-28

Applicant: ANALOG DEVICES, INC.

Inventor： ANALOG DEVICES, INC. ,  JORDAN, Edward, Perry

IPC: H03K19/003

CPC classification number: H03K19/00376 ,  H03K19/01806

Abstract: A level shift circuit for converting an input signal referenced to a positive voltage to an output signal referenced to a lower voltage, such as ground. The level shift circuit includes one or more level shift stages (40, 50) and a reference current generator (60) for causing a constant current to be drawn through each level shift stage. Each level shift stage includes a first transistor (42, 52) having a base for receiving the input signal and a collector connected to the positive voltage (VCC), a second transistor (44, 54) having an emitter coupled to ground, and a level shift resistor (46, 56) coupled between the emitter of the first transistor (42, 52) and the collector of the second transistor (44, 54). The output signal from the collector of the second transistor (44, 54) is typically supplied to a TTL output stage. The reference current generator (60) automatically compensates for temperature and power supply variations, so that the output of the level shift circuit tracks the threshold of the TTL output stage.

公开(公告)号：WO1990013949A1

公开(公告)日：1990-11-15

申请号：PCT/US1990002484

申请日：1990-05-04

Applicant: ANALOG DEVICES, INC.

Inventor： ANALOG DEVICES, INC. ,  TICE, Thomas, E.

IPC: H03M01/36

CPC classification number: H03M1/0604 ,  H03M1/36

Abstract: A flash converter in which means are provided for maintaining a substantially constant collector-base voltage on the input emitter-followers, so as to obviate the distortion caused by variation of the input capacitance with input voltage. The driving source directly drives the base of the emitter-followers and, through a level-shift circuit, also drives the collectors of the emitter-follower transistors.

公开(公告)号：WO1990007234A2

公开(公告)日：1990-06-28

申请号：PCT/US1989005667

申请日：1989-12-11

Applicant: ANALOG DEVICES, INC.

Inventor： ANALOG DEVICES, INC. ,  MANGELSDORF, Christopher, W.

IPC: H03M01/36

CPC classification number: H03M1/363 ,  H03M1/206

Abstract: The apparatus comprises a parallel analog-to-digital converter comprising a matrix of differentially coupled transistor pairs wherein the base of one transistor of each differential pair is coupled to a reference voltage and the base of the other transistor of each differential pair is coupled to the input voltage through a specified offset. In each row of differential pairs, the collectors of the transistors are alternately coupled to first and second row output points. The first and second row output points of each row are coupled to the inverting and non-inverting inputs, respectively of a comparator. Additional comparators are provided for comparing the second row output of each row with the first row output of the succeeding row. The matrix is arranged such that the combination of the comparator outputs is unique for each possible digital level in the full scale range of the converter. Logic circuitry is coupled to the comparator outputs to produce a computer usable code therefrom.

公开(公告)号：WO1990004289A1

公开(公告)日：1990-04-19

申请号：PCT/US1989004350

申请日：1989-10-04

Applicant: ANALOG DEVICES, INC.

Inventor： ANALOG DEVICES, INC. ,  LEWIS, Stephen, R. ,  LEFTON, Scott, A.

IPC: H03M01/78

CPC classification number: H03M1/089 ,  H03M1/1061 ,  H03M1/785

Abstract: The invention provides a monolithic Y-bit resistive-ladder type digital-to-analog converter (DAC) having a unity gain inverting operational amplifier as an input buffer to the resistive ladder segment of the DAC. The reference voltage is applied to the input buffer amplifier. Optional bipolar operation is provided by applying a non-inverted reference voltage to the output of the resistive ladder segment of the DAC through a scale resistance. Analog ground current cancellation is provided by a secondary X-bit R-2R ladder (where X Y) with the non-inverted reference voltage applied to it. The secondary bit ladder is switched in parallel with the top X bits of the main ladder, thereby supplying or sinking roughly the same amount of current as the X most significant bits of the main resistive ladder, but with opposite sense. The effect on the DAC output of the resistance and temperature coefficient of the switches used in the R-2R ladder and elsewhere in the circuitry is minimized by selecting switches appropriately scaled to provide resistances whose sum effect is to cancel each other out. (Particularly, a FET switch biased permanently on is provided at the input of the unity gain inverting operational amplifier). Since the DAC is monolithic, the switches have approximately equal temperature coefficients such that the effect of the switches is consistent at all temperatures.

Abstract translation: 本发明提供了具有单位增益反相运算放大器作为DAC的电阻梯形段的输入缓冲器的单片Y位电阻梯型数模转换器（DAC）。 参考电压被施加到输入缓冲放大器。 通过施加不反转参考电压，通过刻度电阻将DAC施加到DAC的电阻梯形段的输出端来提供可选的双极性操作。 模拟地电流消除由施加了非反相参考电压的次级X位R-2R梯形（其中X Y）提供。 次级梯形图与主梯的顶部X位并行切换，从而提供或吸收与主电阻梯的X个最高有效位大致相同的电流，但具有相反的意义。 通过选择适当缩放的开关来提供R-2R梯形图和电路中其他地方使用的开关的电阻和温度系数对DAC输出的影响，以提供总和效应相互抵消的电阻。 （特别地，在单位增益反相运算放大器的输入处提供永久地偏置的FET开关）。 由于DAC是单片的，所以开关具有大致相等的温度系数，使得开关的效果在所有温度下是一致的。

公开(公告)号：WO1990004284A1

公开(公告)日：1990-04-19

申请号：PCT/US1989004626

申请日：1989-10-16

Applicant: ANALOG DEVICES, INC.

Inventor： ANALOG DEVICES, INC. ,  GERSTENHABER, Moshe ,  LIBERT, Robert, J.

IPC: H03F03/45

CPC classification number: H03F1/56 ,  H03F3/45071

Abstract: A circuit which substantially cancels the input bias current of an operational amplifier having a cascaded NPN-PNP input stage (Q1, Q4). The compensation circuit comprises three transistors. A first NPN transistor (Q6) is coupled to the input stage such that its collector (31) is coupled to the positive voltage source (V+) of the operational amplifier and its emitter (34) is coupled to the emitter (20) of the dual-collector transistor (Q5) of the input stage. The second transistor (Q8), a PNP transitor, has its base (38) coupled to the base (18) of the dual-collector transistor (Q5) and its collector coupled to the bases of both of the NPN transistors (Q1, Q2) of the input stage, which form the inputs of the operational amplifier. This PNP transistor's emitter (49) is coupled to the collector (41) of a third transistor (Q7) which is a dual-collector PNP transistor (Q7). The third transistor (Q7) has an emitter (37) coupled to the positive voltage source (V+) of the operational amplifier and a base and collector (36, 40) coupled to the base (35) of the NPN transistor (Q6) of the compensation circuitry. The areas of the two collector (40, 41) regions of the dual-collector PNP transistor (Q7) are ratioed 2:1. This arrangement of three transistors provides a current to the bases of the input transistors (Q1, Q2) substantially equal to the bias current they require; so virtually no external bias current is drawn from the input signals.

公开(公告)号：WO1986005604A1

公开(公告)日：1986-09-25

申请号：PCT/US1986000055

申请日：1986-01-17

Applicant: ANALOG DEVICES, INC.

Inventor： ANALOG DEVICES, INC. ,  VALLEY, David, P. ,  RYAN, Allan

IPC: G05F01/575

CPC classification number: G05F1/575

Abstract: A voltage/current source includes a loop controller (24) that digitally determines the control signals that must be applied to a driver amplifier (34) to achieve the desired load voltage or current. The analog outputs of current- and voltage-sensing amplifiers (38 and 68) are converted by analog-to-digital converters (52 and 74) to digital feedback signals that the loop controller (24) uses in determining what controls signals to generate. The loop controller (24) keeps the driver-amplifier output voltage equal to the load voltage until switch contacts (30) connect the source to the load so that connection-caused transients are minimized. The loop controller (24) includes read-write memory (25) in which it stores program instructions and operational parameters, so the source can readily change its feedback characteristics. Furthermore, output-voltage limits are readily imposed by software limits on the driver-amplifier input voltage, so no elaborate clamping circuitry at the output port of the source is necessary to prevent output-voltage overshoot.

Abstract translation: 电压/电流源包括环路控制器（24），数字地确定必须施加到驱动器放大器（34）以实现期望的负载电压或电流的控制信号。 电流和电压感测放大器（38和68）的模拟输出由模拟 - 数字转换器（52和74）转换成数字反馈信号，循环控制器（24）在确定什么控制信号产生时使用。 环路控制器（24）保持驱动器放大器输出电压等于负载电压，直到开关触点（30）将源连接到负载，使得连接引起的瞬变最小化。 环路控制器（24）包括读写存储器（25），其中存储程序指令和操作参数，因此源可以容易地改变其反馈特性。 此外，驱动器放大器输入电压的软件限制容易产生输出电压限制，因此在源的输出端口不需要精细的钳位电路来防止输出电压过冲。

公开(公告)号：WO1998028853A1

公开(公告)日：1998-07-02

申请号：PCT/US1997023562

申请日：1997-12-17

Applicant: ANALOG DEVICES, INC.

Inventor： ANALOG DEVICES, INC. ,  MURDEN, Franklin, M. ,  MORELAND, Carl, W. ,  RAY, Harvey, J. ,  ELLIOTT, Michael, R. ,  YOUNG, Marvin, J.

IPC: H03M01/18

CPC classification number: H03M1/186

Abstract: A clock-to-clock auto-ranging ADC operates directly on an analog signal (42a) in the IF band higher to track its gain range on a clock-to-clock basis and produce a digital signal (60) that maintains high resolution of the analog signal without clipping or loss of signal sensitivity. This is accomplished by sampling an analog signal of sufficiently high frequency that a peak detector (61) can accurately determine the maximum signal level over at least one-half a signal period and then reset the signal gain (55) going into the ADC (59) prior to the beginning of the next sampling period. This insures that the analog signal will always be within the range of the ADC.

Abstract translation: 时钟到时钟自动量程ADC直接在IF频带中的模拟信号（42a）上工作，以便在时钟基础上跟踪其增益范围，并产生维持高分辨率的数字信号（60） 模拟信号无剪切或丢失信号灵敏度。 这通过对具有足够高频率的模拟信号进行采样来实现，峰值检测器（61）可以在至少半个信号周期上精确地确定最大信号电平，然后复位进入ADC（59）的信号增益（55） ）在下一个采样周期开始之前。 这确保模拟信号始终在ADC的范围内。

公开(公告)号：WO1998028842A1

公开(公告)日：1998-07-02

申请号：PCT/US1997023998

申请日：1997-12-17

Applicant: ANALOG DEVICES, INC.

Inventor： ANALOG DEVICES, INC. ,  MURDEN, Franklin, M. ,  MORELAND, Carl, W.

IPC: H03G03/00

CPC classification number: H03H11/24 ,  H03G1/0088

Abstract: A digitally controlled programmable attenuator (10) maintains tight phase matching between attenuated signals over wide ranges of frequencies and power levels regardless of the selected attenuation level. This is achieved with a multi-tap ladder network (12) that sets a desired tap-to-tap dB step-size, a plurality of unity gain digitally switched voltage-to-voltage buffers (14) that are connected between the respective taps (16a, 16b, ... 16n) and a common output (18), and a fixed gain stage (20) that sets the overall gain/attenuation of the attenuator. The buffers (14) maintain a high and substantially constant impedance whether turned on or turned off. Phase matching within 0.2 degree at frequencies up to 300 MHZ for 30 dB of gain variation has been realized. The buffers (14) can be implemented with complementary bipolar or BiCMOS processes.

Abstract translation: 数字控制的可编程衰减器（10）在宽范围的频率和功率水平上保持衰减信号之间的紧密相位匹配，而不管选择的衰减水平如何。 这是通过设置期望的抽头分接头dB步长的多抽头梯形网络（12）来实现的，多个单位增益数字开关电压 - 电压缓冲器（14）连接在各个抽头之间 （16a，16b，... 16n）和公共输出（18），以及固定增益级（20），其设定衰减器的总增益/衰减。 缓冲器（14）保持高且基本上恒定的阻抗，无论是打开还是关闭。 已经实现了对于30dB增益变化，频率高达300MHz的0.2度以内的相位匹配。 缓冲器（14）可以用互补双极或BiCMOS工艺来实现。

公开(公告)号：WO1998000879A1

公开(公告)日：1998-01-08

申请号：PCT/US1997011499

申请日：1997-06-30

Applicant: ANALOG DEVICES, INC.

Inventor： ANALOG DEVICES, INC. ,  SZEPESI, Thomas, S.

IPC: H01M10/46

CPC classification number: H02J7/0031 ,  Y10S320/19

Abstract: A battery charger controller monitors the voltage across an associated battery charger's power element (10) and opens a switch (mN1) which inhibits current flow through the controller whenever the voltage across the power element (10) is substantially equal to zero.

Abstract translation: 电池充电器控制器监测相关联的电池充电器的功率元件（10）上的电压，并且当功率元件（10）两端的电压基本上等于零时，打开开关（mN1），其禁止电流流过控制器。

公开(公告)号：WO1997046028A1

公开(公告)日：1997-12-04

申请号：PCT/US1997009235

申请日：1997-05-30

Applicant: ANALOG DEVICES, INC.

Inventor： ANALOG DEVICES, INC. ,  MURRAY, Brian, P. ,  CURRAN, Philip, A. ,  PRENDERGAST, Colm, J. ,  CUMMINS, Timothy, J.

IPC: H04N09/67

CPC classification number: H04N9/83 ,  H04N9/641 ,  H04N9/79 ,  H04N9/793 ,  H04N11/143 ,  H04N11/20

Abstract: A digital-to-analog video encoder (1) method and apparatus having equalization are disclosed. The encoder converts digital video signals into one or more analog video formats using one or more digital-to-analog converters (110, 120, 130). Equalization is provided to compensate for zero order hold effects of the digital-to-analog converters. Equalization is provided to a luminance signal and/or a chroma signal to equalize RGB, composite video, and super VHS video outputs. Multiplexed digital-to-analog converter (80, 90, 100) inputs allow selection of several output formats.

Abstract translation: 公开了一种具有均衡的数模转换视频编码器（1）方法和装置。 编码器使用一个或多个数模转换器（110,120,130）将数字视频信号转换成一个或多个模拟视频格式。 提供均衡以补偿数模转换器的零级保持效应。 将亮度信号和/或色度信号提供均衡以均衡RGB，复合视频和超级VHS视频输出。 多路复用数模转换器（80,90,100）输入允许选择多种输出格式。