公开(公告)号：WO1997045998A2

公开(公告)日：1997-12-04

申请号：PCT/US1997009141

申请日：1997-05-30

Applicant: ANALOG DEVICES, INC.

Inventor： ANALOG DEVICES, INC. ,  MURRAY, Brian, P. ,  CURRAN, Philip, A. ,  PRENDERGAST, Colm, J. ,  CUMMINS, Timothy, J.

IPC: H04N00/00

CPC classification number: H03H17/06 ,  H04N7/0102 ,  H04N9/64

Abstract: A novel finite impulse response filter apparatus and method are disclosed. A multiplexed data stream composed of two or more data streams is provided as an input to a tapped delay line. Weight and sum operators are connected to the even or odd delay line taps and generate a filtered output. The filter operates on one data stream per cycle and generates a multiplexed output. In another form, odd weight and sum operators are connected to and odd taps and even weight and sum operators are connected to the odd taps generating two filtered outputs. The filter operates on both data streams in each cycle and generates two multiplexed outputs. A crossbar switch is disclosed for parsing the multiplexed outputs into the constituent filtered data streams. The filter stages may be cascaded.

Abstract translation: 公开了一种新颖的有限脉冲响应滤波器装置和方法。 提供由两个或多个数据流组成的复用数据流作为抽头延迟线的输入。 重量和和运算符连接到偶数或奇数延迟线抽头，并生成滤波输出。 滤波器对每个周期的一个数据流进行操作，并产生多路输出。 在另一种形式中，奇数和和运算符连接到奇数抽头，甚至重量和和运算符连接到产生两个滤波输出的奇数抽头。 滤波器在每个周期中对两个数据流进行操作，并生成两个多路复用输出。 公开了一种用于将多路复用输出解析为组成滤波数据流的交叉开关。 过滤器级可以级联。

公开(公告)号：WO2008118286A2

公开(公告)日：2008-10-02

申请号：PCT/US2008/003153

申请日：2008-03-11

Applicant: ANALOG DEVICES, INC. ,  WILSON, James ,  STEIN, Yosef ,  KABLOTSKY, Joshua ,  PRENDERGAST, Colm, J. ,  YUKNA, Gregory, M. ,  MAYER, Christopher, M.

Inventor： WILSON, James ,  STEIN, Yosef ,  KABLOTSKY, Joshua ,  PRENDERGAST, Colm, J. ,  YUKNA, Gregory, M. ,  MAYER, Christopher, M.

IPC: G06F17/17

CPC classification number: H04N19/86 ,  H04N19/117 ,  H04N19/14 ,  H04N19/159 ,  H04N19/176 ,  H04N19/42 ,  H04N19/61

Abstract: Finite impulse response filtering is achieved by broadcasting to at least one compute unit an instruction having a plurality of data samples, a conditional field associated with each compute unit, and a set of operator values for operating on each data sample; providing a function of each the data sample in accordance with an associated set of operator values identified by the conditional field; and combining the functions to obtain an intermediate finite impulse response of the data samples.

Abstract translation: 通过向至少一个计算单元广播具有多个数据样本的指令，与每个计算单元相关联的条件字段以及用于在每个数据样本上操作的一组运算符值来实现有限冲激响应滤波; 根据由条件字段识别的一组相关的操作者值提供每个数据样本的函数; 并组合函数以获得数据样本的中间有限脉冲响应。

公开(公告)号：WO2007050361A2

公开(公告)日：2007-05-03

申请号：PCT/US2006/040510

申请日：2006-10-17

Applicant: ANALOG DEVICES, INC. ,  WILSON, James ,  KABLOTSKY, Joshua, A. ,  STEIN, Yosef ,  PRENDERGAST, Colm, J. ,  YUKNA, Gregory, M. ,  MAYER, Christopher, M.

Inventor： WILSON, James ,  KABLOTSKY, Joshua, A. ,  STEIN, Yosef ,  PRENDERGAST, Colm, J. ,  YUKNA, Gregory, M. ,  MAYER, Christopher, M.

IPC: G06F15/00

CPC classification number: G06F9/3001 ,  G06F9/345 ,  G06F9/3885

Abstract: Reducing pipeline stall between a compute unit and address unit in a processor can be accomplished by computing results in a compute unit in response to instructions of an algorithm; storing in a local random access memory array in a compute unit predetermined sets of functions, related to the computed results for predetermined sets of instructions of the algorithm; and providing within the compute unit direct mapping of computed results to related function.

Abstract translation: 减少处理器中的计算单元和地址单元之间的流水线停顿可以通过响应于算法的指令在计算单元中计算结果来实现; 在计算单元中存储与本算法的预定指令集合的计算结果相关的预定函数集的局部随机存取存储器阵列; 并且在计算单元内提供计算结果与相关功能的直接映射。

公开(公告)号：WO2004068815A1

公开(公告)日：2004-08-12

申请号：PCT/US2004/002082

申请日：2004-01-27

Applicant: ANALOG DEVICES, INC. ,  FAGUE, Daniel, E. ,  LIPTAY, Thomas, J. ,  PRENDERGAST, Colm, J. ,  BALBONI, Edmund, J.

Inventor： FAGUE, Daniel, E. ,  LIPTAY, Thomas, J. ,  PRENDERGAST, Colm, J. ,  BALBONI, Edmund, J.

IPC: H04L27/152

CPC classification number: H04L27/0014 ,  H04L27/1525 ,  H04L2027/003 ,  H04L2027/0095

Abstract: Frequency offsets between a received carrier signal and a receiver's LO frequency are compensated by deter­mining the offset and adjusting the phase of a demodulated signal derived from the modulated carrier. For frequency offsets that produce DC voltage offsets in I and Q components of the demodulated signal, the phase correc­tion is implemented by operating upon the I and Q compo­nents with phase rotation operators in the form of sinθ and cosθ, where θ is an angle whose tangent is the result of dividing the Q by the I frequency offsets.

Abstract translation: 通过确定偏移并调整从调制载波导出的解调信号的相位来补偿接收到的载波信号和接收机的LO频率之间的频率偏移。 对于在解调信号的I和Q分量中产生直流电压偏移的频率偏移，相位校正是通过对具有相位旋转算子的I和Q分量进行运算来实现的，相位旋转运算符以辛特尔和costheta的形式，其中θ是一个角度， 是将Q除以I频率偏移的结果。

公开(公告)号：WO1997046028A1

公开(公告)日：1997-12-04

申请号：PCT/US1997009235

申请日：1997-05-30

Applicant: ANALOG DEVICES, INC.

Inventor： ANALOG DEVICES, INC. ,  MURRAY, Brian, P. ,  CURRAN, Philip, A. ,  PRENDERGAST, Colm, J. ,  CUMMINS, Timothy, J.

IPC: H04N09/67

CPC classification number: H04N9/83 ,  H04N9/641 ,  H04N9/79 ,  H04N9/793 ,  H04N11/143 ,  H04N11/20

Abstract: A digital-to-analog video encoder (1) method and apparatus having equalization are disclosed. The encoder converts digital video signals into one or more analog video formats using one or more digital-to-analog converters (110, 120, 130). Equalization is provided to compensate for zero order hold effects of the digital-to-analog converters. Equalization is provided to a luminance signal and/or a chroma signal to equalize RGB, composite video, and super VHS video outputs. Multiplexed digital-to-analog converter (80, 90, 100) inputs allow selection of several output formats.

Abstract translation: 公开了一种具有均衡的数模转换视频编码器（1）方法和装置。 编码器使用一个或多个数模转换器（110,120,130）将数字视频信号转换成一个或多个模拟视频格式。 提供均衡以补偿数模转换器的零级保持效应。 将亮度信号和/或色度信号提供均衡以均衡RGB，复合视频和超级VHS视频输出。 多路复用数模转换器（80,90,100）输入允许选择多种输出格式。

公开(公告)号：EP1941378A2

公开(公告)日：2008-07-09

申请号：EP06817042.2

申请日：2006-10-17

Applicant: Analog Devices, Inc.

Inventor： WILSON, James ,  KABLOTSKY, Joshua, A. ,  STEIN, Yosef ,  PRENDERGAST, Colm, J. ,  YUKNA, Gregory, M. ,  MAYER, Christopher, M.

IPC: G06F15/00

CPC classification number: G06F9/3001 ,  G06F9/345 ,  G06F9/3885

Abstract: Reducing pipeline stall between a compute unit and address unit in a processor can be accomplished by computing results in a compute unit in response to instructions of an algorithm; storing in a local random access memory array in a compute unit predetermined sets of functions, related to the computed results for predetermined sets of instructions of the algorithm; and providing within the compute unit direct mapping of computed results to related function.

公开(公告)号：EP1999607A2

公开(公告)日：2008-12-10

申请号：EP07752132.6

申请日：2007-03-01

Applicant: Analog Devices, Inc.

Inventor： WILSON, James ,  KABLOTSKY, Joshua, A. ,  STEIN, Yossef ,  PRENDERGAST, Colm, J. ,  YUKNA, Gregory, M. ,  MAYER, Christopher, M. ,  HAYDEN, John, A.

IPC: G06F15/00

CPC classification number: G06F9/30109 ,  G06F7/57 ,  G06F7/766 ,  G06F7/768 ,  G06F9/30032 ,  G06F9/30036 ,  G06F9/30043 ,  G06F9/3013

Abstract: Accommodating a processor to process a number of different data formats includes loading a data word in a first format from a first storage device; reordering, before it reaches the arithmetic unit, the first format of the data word to a second format compatible with the native order of the arithmetic unit; and vector processing the data word in the arithmetic unit.