公开(公告)号：US11855197B2

公开(公告)日：2023-12-26

申请号：US17580127

申请日：2022-01-20

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Shesh Mani Pandey ,  Alexander M. Derrickson ,  Judson R. Holt ,  Vibhor Jain

IPC: H01L29/737 ,  H01L29/08 ,  H01L29/10 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66

CPC classification number: H01L29/7371 ,  H01L29/0821 ,  H01L29/1004 ,  H01L29/41708 ,  H01L29/42304 ,  H01L29/66234

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to vertical bipolar transistors and methods of manufacture. The structure includes: an intrinsic base region comprising semiconductor-on-insulator material; a collector region confined within an insulator layer beneath the semiconductor-on-insulator material; an emitter region above the intrinsic base region; and an extrinsic base region above the intrinsic base region.

公开(公告)号：US11799021B2

公开(公告)日：2023-10-24

申请号：US17450842

申请日：2021-10-14

Applicant: GlobalFoundries U.S. Inc.

Inventor： Vibhor Jain ,  Alexander M. Derrickson ,  Judson R. Holt

IPC: H01L29/735 ,  H01L29/08 ,  H01L27/12 ,  H01L29/66 ,  H01L29/06

CPC classification number: H01L29/735 ,  H01L27/1203 ,  H01L29/0649 ,  H01L29/0808 ,  H01L29/0821 ,  H01L29/6625

Abstract: Embodiments of the disclosure provide a lateral bipolar transistor structure with a marker layer for emitter and collector terminals. A lateral bipolar transistor structure according to the disclosure includes a semiconductor layer over an insulator layer. The semiconductor layer includes an emitter/collector (E/C) region having a first doping type and an intrinsic base region adjacent the E/C region and having a second doping type opposite the first doping type. A marker layer is on the E/C region of the semiconductor layer, and a raised E/C terminal is on the marker layer. An extrinsic base is on the intrinsic base region of the semiconductor layer, and a spacer is horizontally between the raised E/C terminal and the extrinsic base.

公开(公告)号：US11777019B2

公开(公告)日：2023-10-03

申请号：US17586862

申请日：2022-01-28

Applicant: GlobalFoundries U.S. Inc.

Inventor： Hong Yu ,  Vibhor Jain ,  Judson R. Holt

IPC: H01L29/737 ,  H01L29/08 ,  H01L29/66 ,  H01L29/735

CPC classification number: H01L29/737 ,  H01L29/0821 ,  H01L29/66242 ,  H01L29/735

Abstract: Disclosed is a semiconductor structure including a device, such as a lateral heterojunction bipolar transistor (HBT), made up of a combination of at least three different semiconductor materials with different bandgap sizes for improved performance. In the device, a base layer of the base region can be positioned laterally between a collector layer of a collector region and an emitter layer of an emitter region and can be physically separated therefrom by buffer layers. The base layer can be made of a narrow bandgap semiconductor material, the collector layer and, optionally, the emitter layer can be made of a wide bandgap semiconductor material, and the buffer layers can be made of a semiconductor material with a bandgap between that of the narrow bandgap semiconductor material and the wide bandgap semiconductor material. Also disclosed herein is a method of forming the structure.

公开(公告)号：US11749747B2

公开(公告)日：2023-09-05

申请号：US17574661

申请日：2022-01-13

Applicant: GlobalFoundries U.S. Inc.

Inventor： Judson R. Holt ,  Vibhor Jain ,  Jeffrey B. Johnson ,  John J. Pekarik

IPC: H01L29/737 ,  H01L29/66 ,  H01L21/763 ,  H01L29/06

CPC classification number: H01L29/7371 ,  H01L21/763 ,  H01L29/0642 ,  H01L29/66242

Abstract: Embodiments of the disclosure provide a bipolar transistor structure with a collector on a polycrystalline isolation layer. A polycrystalline isolation layer may be on a substrate, and a collector layer may be on the polycrystalline isolation layer. The collector layer has a first doping type and includes a polycrystalline semiconductor. A base layer is on the collector layer and has a second doping type opposite the first doping type. An emitter layer is on the base layer and has the first doping type. A material composition of the doped collector region is different from a material composition of the base layer.

公开(公告)号：US11710771B2

公开(公告)日：2023-07-25

申请号：US17524043

申请日：2021-11-11

Applicant: GlobalFoundries U.S. Inc.

Inventor： Alexander Derrickson ,  Judson R. Holt ,  Haiting Wang ,  Jagar Singh ,  Vibhor Jain

IPC: H01L29/10 ,  H01L29/08 ,  H01L29/66 ,  H01L29/735 ,  H01L29/737

CPC classification number: H01L29/1008 ,  H01L29/0808 ,  H01L29/0817 ,  H01L29/0821 ,  H01L29/6625 ,  H01L29/6656 ,  H01L29/66242 ,  H01L29/66553 ,  H01L29/735 ,  H01L29/737

Abstract: Structures for a bipolar junction transistor and methods of forming a structure for a bipolar junction transistor. The structure includes an emitter having a raised portion, a collector having a raised portion, and a base having a base layer and an extrinsic base layer stacked with the base layer. The base layer and the extrinsic base layer are positioned in a lateral direction between the raised portion of the emitter and the raised portion of the collector, the base layer has a first width in the lateral direction, the extrinsic base layer has a second width in the lateral direction, and the second width is greater than the first width.

公开(公告)号：US20230102573A1

公开(公告)日：2023-03-30

申请号：US17586862

申请日：2022-01-28

Applicant: GlobalFoundries U.S. Inc.

Inventor： Hong Yu ,  Vibhor Jain ,  Judson R. Holt

IPC: H01L29/737 ,  H01L29/735 ,  H01L29/08 ,  H01L29/66

Abstract: Disclosed is a semiconductor structure including a device, such as a lateral heterojunction bipolar transistor (HBT), made up of a combination of at least three different semiconductor materials with different bandgap sizes for improved performance. In the device, a base layer of the base region can be positioned laterally between a collector layer of a collector region and an emitter layer of an emitter region and can be physically separated therefrom by buffer layers. The base layer can be made of a narrow bandgap semiconductor material, the collector layer and, optionally, the emitter layer can be made of a wide bandgap semiconductor material, and the buffer layers can be made of a semiconductor material with a bandgap between that of the narrow bandgap semiconductor material and the wide bandgap semiconductor material. Also disclosed herein is a method of forming the structure.

公开(公告)号：US20230065924A1

公开(公告)日：2023-03-02

申请号：US17511613

申请日：2021-10-27

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Alexander M. Derrickson ,  Haiting Wang ,  Judson R. Holt ,  Vibhor Jain ,  Richard F. Taylor, III

IPC: H01L29/737 ,  H01L29/08 ,  H01L29/10 ,  H01L29/165 ,  H01L21/02 ,  H01L21/225 ,  H01L29/66

Abstract: Disclosed is a semiconductor structure including a lateral heterojunction bipolar transistor (HBT). The structure includes a substrate (e.g., a silicon substrate), an insulator layer on the substrate, and a semiconductor layer (e.g., a silicon germanium layer) on the insulator layer. The structure includes a lateral HBT with three terminals including a collector, an emitter, and a base, which is positioned laterally between the collector and the emitter and which can include a silicon germanium intrinsic base region for improved performance. Additionally, the collector and/or the emitter includes: a first region, which is epitaxially grown within a trench that extends through the semiconductor layer and the insulator layer to the substrate; and a second region, which is epitaxially grown on the first region. The connection(s) of the collector and/or the emitter to the substrate effectively form thermal exit path(s) and minimize self-heating. Also disclosed is a method for forming the structure.

公开(公告)号：US20230065785A1

公开(公告)日：2023-03-02

申请号：US17555561

申请日：2021-12-20

Applicant: GlobalFoundries U.S. Inc.

Inventor： Jagar Singh ,  Alexander M. Derrickson ,  Alvin J. Joseph ,  Andreas Knorr ,  Judson R. Holt

IPC: H01L29/737 ,  H01L29/08 ,  H01L29/10 ,  H01L29/66

Abstract: Disclosed is a semiconductor structure with a lateral bipolar junction transistor (BJT). This semiconductor structure can be readily integrated into advanced silicon-on-insulator (SOI) technology platforms. Furthermore, to maintain or improve upon performance characteristics (e.g., cut-off frequency (fT)/maximum oscillation frequency (fmax) and beta cut-off frequency) that would otherwise be negatively impacted due to changing of the orientation of the BJT from vertical to lateral, the semiconductor structure can further include a dielectric stress layer (e.g., a tensilely strained layer in the case of an NPN-type transistor or a compressively strained layer in the case of a PNP-type transistor) partially covering the lateral BJT for charge carrier mobility enhancement and the lateral BJT can be configured as a lateral heterojunction bipolar transistor (HBT). Also disclosed is a method for forming the semiconductor structure.

公开(公告)号：US20230058451A1

公开(公告)日：2023-02-23

申请号：US17450842

申请日：2021-10-14

Applicant: GlobalFoundries U.S. Inc.

Inventor： Vibhor Jain ,  Alexander M. Derrickson ,  Judson R. Holt

IPC: H01L29/735 ,  H01L29/08 ,  H01L29/06 ,  H01L29/66 ,  H01L27/12

Abstract: Embodiments of the disclosure provide a lateral bipolar transistor structure with a marker layer for emitter and collector terminals. A lateral bipolar transistor structure according to the disclosure includes a semiconductor layer over an insulator layer. The semiconductor layer includes an emitter/collector (E/C) region having a first doping type and an intrinsic base region adjacent the E/C region and having a second doping type opposite the first doping type. A marker layer is on the E/C region of the semiconductor layer, and a raised E/C terminal is on the marker layer. An extrinsic base is on the intrinsic base region of the semiconductor layer, and a spacer is horizontally between the raised E/C terminal and the extrinsic base.

公开(公告)号：US11094834B2

公开(公告)日：2021-08-17

申请号：US16790084

申请日：2020-02-13

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Qizhi Liu ,  Vibhor Jain ,  John J. Pekarik ,  Judson R. Holt

IPC: H01L21/00 ,  H01L29/808 ,  H01L29/06 ,  H01L29/10 ,  H01L29/08 ,  H01L21/02 ,  H01L21/225 ,  H01L29/66

Abstract: A junction field effect transistor (JFET) structure includes a doped polysilicon gate over a channel region of a semiconductor layer. The doped polysilicon gate has a first doping type. A raised epitaxial source is on the source region of the semiconductor layer and adjacent a first sidewall of the doped polysilicon gate, and has a second doping type opposite the first doping type. A raised epitaxial drain is on the drain region of the semiconductor layer and adjacent a second sidewall of the doped polysilicon gate, and has the second doping type. A doped semiconductor region is within the channel region of the semiconductor layer and extending from the source region to the drain region, and a non-conductive portion of the semiconductor layer is within the channel region to separate the doped semiconductor region from the doped polysilicon gate.