公开(公告)号：US11417775B2

公开(公告)日：2022-08-16

申请号：US16043593

申请日：2018-07-24

Applicant: Intel Corporation

Inventor： Shriram Shivaraman ,  Van H. Le ,  Abhishek A. Sharma ,  Gilbert W. Dewey ,  Benjamin Chu-Kung ,  Miriam R. Reshotko ,  Jack T. Kavalieros ,  Tahir Ghani

IPC: H01L29/786 ,  H01L29/66 ,  H01L29/06 ,  H01L29/423 ,  H01L21/02 ,  H01L21/768 ,  H01L23/00

Abstract: Disclosed herein are transistor gate-channel arrangements that may be implemented in nanowire thin film transistors (TFTs) with textured semiconductors, and related methods and devices. An example transistor gate-channel arrangement may include a substrate, a channel material that includes a textured thin film semiconductor material shaped as a nanowire, a gate dielectric that at least partially wraps around the nanowire, and a gate electrode material that wraps around the gate dielectric. Implementing textured thin film semiconductor channel materials shaped as a nanowire and having a gate stack of a gate dielectric and a gate electrode material wrapping around the nanowire advantageously allows realizing gate all-around or bottom-gate transistor architectures for TFTs with textured semiconductor channel materials.

公开(公告)号：US11387366B2

公开(公告)日：2022-07-12

申请号：US16634517

申请日：2017-09-27

Applicant: Intel Corporation

Inventor： Abhishek A. Sharma ,  Van H. Le ,  Jack T. Kavalieros ,  Tahir Ghani ,  Gilbert Dewey ,  Shriram Shivaraman ,  Inanc Meric ,  Benjamin Chu-Kung

IPC: H01L29/786 ,  H01L27/108 ,  H01L27/24 ,  H01L29/51 ,  H01L29/66

Abstract: Embodiments herein describe techniques for a semiconductor device, which may include a substrate, a metallic encapsulation layer above the substrate, and a gate electrode above the substrate and next to the metallic encapsulation layer. A channel layer may be above the metallic encapsulation layer and the gate electrode, where the channel layer may include a source area and a drain area. In addition, a source electrode may be coupled to the source area, and a drain electrode may be coupled to the drain area. Other embodiments may be described and/or claimed.

公开(公告)号：US11264512B2

公开(公告)日：2022-03-01

申请号：US16024682

申请日：2018-06-29

Applicant: Intel Corporation

Inventor： Gilbert Dewey ,  Aaron Lilak ,  Van H. Le ,  Abhishek A. Sharma ,  Tahir Ghani ,  Willy Rachmady ,  Rishabh Mehandru ,  Nazila Haratipour ,  Jack T. Kavalieros ,  Benjamin Chu-Kung ,  Seung Hoon Sung ,  Shriram Shivaraman

IPC: H01L29/786 ,  H01L29/66

Abstract: Thin film transistors having U-shaped features are described. In an example, integrated circuit structure including a gate electrode above a substrate, the gate electrode having a trench therein. A channel material layer is over the gate electrode and in the trench, the channel material layer conformal with the trench. A first source or drain contact is coupled to the channel material layer at a first end of the channel material layer outside of the trench. A second source or drain contact is coupled to the channel material layer at a second end of the channel material layer outside of the trench.

公开(公告)号：US11177376B2

公开(公告)日：2021-11-16

申请号：US16258422

申请日：2019-01-25

Applicant: Intel Corporation

Inventor： Sansaptak Dasgupta ,  Han Wui Then ,  Sanaz K. Gardner ,  Marko Radosavljevic ,  Seung Hoon Sung ,  Benjamin Chu-Kung ,  Robert S. Chau

IPC: H01L29/778 ,  H01L29/66 ,  H01L21/02 ,  H01L29/417 ,  H01L29/06

Abstract: III-N semiconductor heterostructures on III-N epitaxial islands laterally overgrown from a mesa of a silicon substrate. An IC may include a III-N semiconductor device disposed on the III-N epitaxial island overhanging the silicon mesa and may further include a silicon-based MOSFET monolithically integrated with the III-N device. Lateral epitaxial overgrowth from silicon mesas may provide III-N semiconductor regions of good crystal quality upon which transistors or other active semiconductor devices may be fabricated. Overhanging surfaces of III-N islands may provide multiple device layers on surfaces of differing polarity. Spacing between separate III-N islands may provide mechanical compliance to an IC including III-N semiconductor devices. Undercut of the silicon mesa may be utilized for transfer of III-N epitaxial islands to alternative substrates.

公开(公告)号：US11158711B2

公开(公告)日：2021-10-26

申请号：US16645405

申请日：2017-12-27

Applicant: Intel Corporation

Inventor： Abhishek A. Sharma ,  Van H. Le ,  Li Huey Tan ,  Tristan Tronic ,  Benjamin Chu-Kung

IPC: H01L29/417 ,  H01L29/66 ,  H01L29/786

Abstract: Embodiments herein describe techniques for a thin-film transistor (TFT), which may include a gate electrode above a substrate and a channel layer above the gate electrode. A source electrode may be above the channel layer and adjacent to a source area of the channel layer, and a drain electrode may be above the channel layer and adjacent to a drain area of the channel layer. A passivation layer may be above the channel layer and between the source electrode and the drain electrode, and a top dielectric layer may be above the gate electrode, the channel layer, the source electrode, the drain electrode, and the passivation layer. In addition, an air gap may be above the passivation layer and below the top dielectric layer, and between the source electrode and the drain electrode. Other embodiments may be described and/or claimed.

公开(公告)号：US11081570B2

公开(公告)日：2021-08-03

申请号：US16326845

申请日：2016-09-28

Applicant: INTEL CORPORATION

Inventor： Karthik Jambunathan ,  Glenn A. Glass ,  Anand S. Murthy ,  Jack T. Kavalieros ,  Seung Hoon Sung ,  Benjamin Chu-Kung ,  Tahir Ghani

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/10

Abstract: Integrated circuit transistor structures are disclosed that include a gate structure that is lattice matched to the underlying channel. In particular, the gate dielectric is lattice matched to the underlying semiconductor channel material, and in some embodiments, so is the gate electrode. In an example embodiment, single crystal semiconductor channel material and single crystal gate dielectric material that are sufficiently lattice matched to each other are epitaxially deposited. In some cases, the gate electrode material may also be a single crystal material that is lattice matched to the semiconductor channel material, thereby allowing the gate electrode to impart strain on the channel via the also lattice matched gate dielectric. A gate dielectric material that is lattice matched to the channel material can be used to reduce interface trap density (Dit). The techniques can be used in both planar and non-planar (e.g., finFET and nanowire) metal oxide semiconductor (MOS) transistor architectures.

公开(公告)号：US10998270B2

公开(公告)日：2021-05-04

申请号：US16337794

申请日：2016-10-28

Applicant: INTEL CORPORATION

Inventor： Seung Hoon Sung ,  Glenn A. Glass ,  Van H. Le ,  Ashish Agrawal ,  Benjamin Chu-Kung ,  Anand S. Murthy ,  Jack T. Kavalieros

IPC: H01L23/535 ,  H01L29/78 ,  H01L29/417 ,  H01L29/423 ,  H01L27/092 ,  H01L21/768 ,  H01L21/8238

Abstract: Techniques are disclosed for forming transistor devices having reduced interfacial resistance in a local interconnect. The local interconnect can be a material having similar composition to that of the source/drain material. That composition can be a metal alloy of a group IV element such as nickel germanide. The local interconnect of the semiconductor integrated circuit can function in the absence of barrier and liner layers. The devices can be used on MOS transistors including PMOS transistors.

公开(公告)号：US10784170B2

公开(公告)日：2020-09-22

申请号：US16372272

申请日：2019-04-01

Applicant: Intel Corporation

Inventor： Marko Radosavljevic ,  Ravi Pillarisetty ,  Gilbert Dewey ,  Niloy Mukherjee ,  Jack Kavalieros ,  Willy Rachmady ,  Van Le ,  Benjamin Chu-Kung ,  Matthew Metz ,  Robert Chau

IPC: H01L21/84 ,  H01L21/8258 ,  H01L27/092 ,  H01L29/06 ,  H01L29/16 ,  H01L29/20 ,  H01L21/306 ,  H01L21/02 ,  H01L21/8238 ,  H01L29/423 ,  H01L29/786 ,  H01L27/12 ,  B82Y10/00 ,  H01L29/66 ,  H01L29/775 ,  H01L29/78 ,  H01L29/205

Abstract: Architectures and techniques for co-integration of heterogeneous materials, such as group III-V semiconductor materials and group IV semiconductors (e.g., Ge) on a same substrate (e.g. silicon). In embodiments, multi-layer heterogeneous semiconductor material stacks having alternating nanowire and sacrificial layers are employed to release nanowires and permit formation of a coaxial gate structure that completely surrounds a channel region of the nanowire transistor. In embodiments, individual PMOS and NMOS channel semiconductor materials are co-integrated with a starting substrate having a blanket layers of alternating Ge/III-V layers. In embodiments, vertical integration of a plurality of stacked nanowires within an individual PMOS and individual NMOS device enable significant drive current for a given layout area.

公开(公告)号：US10692973B2

公开(公告)日：2020-06-23

申请号：US16474446

申请日：2017-04-01

Applicant: INTEL CORPORATION

Inventor： Glenn A. Glass ,  Anand S. Murthy ,  Karthik Jambunathan ,  Benjamin Chu-Kung ,  Seung Hoon Sung ,  Jack T. Kavalieros ,  Tahir Ghani ,  Harold W. Kennel

IPC: H01L21/00 ,  H01L27/00 ,  H01L29/00 ,  H01L29/10 ,  H01L21/02 ,  H01L21/22 ,  H01L21/768 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78

Abstract: Techniques are disclosed for forming germanium (Ge)-rich channel transistors including one or more dopant diffusion barrier elements. The introduction of one or more dopant diffusion elements into at least a portion of a given source/drain (S/D) region helps inhibit the undesired diffusion of dopant (e.g., B, P, or As) into the adjacent Ge-rich channel region. In some embodiments, the elements that may be included in a given S/D region to help prevent the undesired dopant diffusion include at least one of tin and relatively high silicon. Further, in some such embodiments, carbon may also be included to help prevent the undesired dopant diffusion. In some embodiments, the one or more dopant diffusion barrier elements may be included in an interfacial layer between a given S/D region and the Ge-rich channel region and/or throughout at least a majority of a given S/D region. Numerous embodiments, configurations, and variations will be apparent.

公开(公告)号：US20200185504A1

公开(公告)日：2020-06-11

申请号：US16633603

申请日：2017-09-27

Applicant: Intel Corporation

Inventor： Abhishek A. Sharma ,  Van H. Le ,  Jack T. Kavalieros ,  Tahir Ghani ,  Gilbert Dewey ,  Shriram Shivaraman ,  Sean T. Ma ,  Benjamin Chu-Kung

IPC: H01L29/423 ,  H01L29/786 ,  H01L29/51 ,  H01L21/28 ,  H01L29/66

Abstract: An embodiment includes an apparatus comprising: a substrate; a thin film transistor (TFT) comprising: source, drain, and gate contacts; a semiconductor material, comprising a channel, between the substrate and the gate contact; a gate dielectric layer between the gate contact and the channel; and an additional layer between the channel and the substrate; wherein (a)(i) the channel includes carriers selected from the group consisting of hole carriers or electron carriers, (a)(ii) the additional layer includes an insulator material that includes charged particles having a polarity equal to a polarity of the carriers. Other embodiments are described herein.