公开(公告)号：WO1998027595A1

公开(公告)日：1998-06-25

申请号：PCT/US1997021447

申请日：1997-11-24

Applicant: INTEL CORPORATION

Inventor： INTEL CORPORATION ,  BOHR, Mark, T. ,  MOHSEN, Alavi ,  TSAI, Min-Chun

IPC: H01L29/00

CPC classification number: H01L23/5256 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A fusible link device disposed on a semiconductor substrate for providing discretionary changes in resistance. The fusible link device of the invention includes a polysilicon layer (105) having a first resistance. A silicide layer (104) formed on the polysilicon layer has a second, lower resistance and includes a fuse region having a first notched region (130) narrower than the center of the fuse region, a first contact region (120) electrically coupled to one end of the fuse region and a second contact region (121) electrically coupled to an opposite end of the fuse region. The silicide layer agglomerates to form an electrical discontinuity in the fuse region (usually in the notched region) in response to a current greater than or equal to a predetermined programming current flowing between the contact regions, such that the resistance of the fusible link device can be selectively increased.

Abstract translation: 一种设置在半导体衬底上的可熔连接装置，用于提供任意改变的电阻。 本发明的可熔连接装置包括具有第一电阻的多晶硅层（105）。 形成在多晶硅层上的硅化物层（104）具有第二较低电阻并且包括具有比熔丝区域的中心窄的第一缺口区域（130）的熔丝区域，电耦合到一个第一接触区域 熔丝区域的端部和电耦合到熔丝区域的相对端的第二接触区域（121）。 硅化物层响应于大于或等于在接触区域之间流动的预定编程电流的电流而在熔断器区域（通常在缺口区域中）形成电中断，使得可熔连接装置的电阻可以 有选择地增加。

公开(公告)号：WO1998027493A1

公开(公告)日：1998-06-25

申请号：PCT/US1997021744

申请日：1997-12-01

Applicant: INTEL CORPORATION

Inventor： INTEL CORPORATION ,  WU, William, S. ,  PAWLOWSKI, Stephen, S. ,  MACWILLIAMS, Peter, D.

IPC: G06F13/14

CPC classification number: G06F12/1036 ,  G06F2212/682

Abstract: As shown in the figure, the translation lookaside buffer, or TLB (111, 115), shootdown operation of the present invention provides for a TLB (111, 115) flush transaction communicated between multiple processors (2) on a host bus (120). One microprocessor (2) issues a TLB (111, 115) flush request on the host bus (120). The TLB (111, 115) flush request includes a page number. The microprocessors (2) receiving the request invalidate the TLB (111, 115) entry corresponding to the page number.

Abstract translation: 如图所示，本发明的翻转后备缓冲器或TLB（111,115）击倒操作提供在主机总线（120）上的多个处理器（2）之间传送的TLB（111,115）刷新事务， 。 一个微处理器（2）在主机总线（120）上发出一个TLB（111,115）刷新请求。 TLB（111,115）刷新请求包括页码。 接收请求的微处理器（2）使与页码对应的TLB（111,115）条目无效。

公开(公告)号：WO1998025201A1

公开(公告)日：1998-06-11

申请号：PCT/US1997021547

申请日：1997-11-26

Applicant: INTEL CORPORATION

Inventor： INTEL CORPORATION ,  SHARANGPANI, Harshvardhan

IPC: G06F07/38

CPC classification number: G06F9/30185 ,  G06F7/483 ,  G06F9/30014

Abstract: A processor (100) contains a storage area (120) for a dynamic rounding mode control value, and a circuit (124) coupled to the storage area configured to execute an instruction using a rounding mode. When the instruction is a first predetermined instruction, a first predetermined rounding mode is used during execution of the instruction. When the instruction is not the first predetermined instruction and the rounding mode specified by the instruction is not a dynamic override, the circuit executes the instruction using a rounding mode (110) specified by the instruction. When the instruction is not the first predetermined instruction and the rounding mode specified by the instruction is the dynamic override, the circuit executes the instruction using a rounding mode specified by the dynamic rounding mode control value (115).

Abstract translation: 处理器（100）包括用于动态舍入模式控制值的存储区域（120）和耦合到存储区域的电路（124），其被配置为使用舍入模式执行指令。 当指令是第一预定指令时，在执行指令期间使用第一预定舍入模式。 当指令不是第一预定指令并且由指令指定的舍入模式不是动态覆盖时，电路使用由指令指定的舍入模式（110）来执行指令。 当指令不是第一预定指令并且由指令指定的舍入模式是动态覆盖时，电路使用由动态舍入模式控制值（115）指定的舍入模式来执行指令。

公开(公告)号：WO1998021709A1

公开(公告)日：1998-05-22

申请号：PCT/US1997014026

申请日：1997-08-08

Applicant: INTEL CORPORATION

Inventor： INTEL CORPORATION ,  SIMMERS, Charles, Russell

IPC: G09G05/00

CPC classification number: G06F1/3265 ,  G06F1/32 ,  G06F3/147 ,  G09G3/3644 ,  G09G2330/021 ,  G09G2360/04 ,  H04M1/0214 ,  H04M2250/16 ,  H04W52/027 ,  Y02D10/153 ,  Y02D70/00

Abstract: An apparatus for conserving power in information devices with dual functions. A single display panel (200) is logically split into two sub-panels (202, 204). Each subpanel can be powered up or down separately as is required by the function of the device. The display panel (200) has a plurality of improved segment drivers (120, 122) which are provided power signals enabling the set of segment drivers corresponding to a sub-panel to be separately powered. In systems with two separate display panels, each of the panels may be powered up or down by the use of similar improved segment drivers as necessary.

Abstract translation: 一种用于在具有双重功能的信息设备中节省功率的装置。 单个显示面板（200）在逻辑上分为两个子面板（202,204）。 每个子面板可以按照设备功能所要求的单独上电或下电。 所述显示面板（200）具有多个改进的分段驱动器（120,122），所述多个改进的分段驱动器提供功率信号，使得与子面板相对应的分组驱动器组能够单独供电。 在具有两个独立显示面板的系统中，每个面板可以根据需要使用类似的改进的段驱动器来上电或下电。

公开(公告)号：WO1998021659A1

公开(公告)日：1998-05-22

申请号：PCT/US1997014024

申请日：1997-08-08

Applicant: INTEL CORPORATION

Inventor： INTEL CORPORATION ,  SAGER, David, J.

IPC: G06F12/00

CPC classification number: G06F12/0893 ,  G06F9/383 ,  G06F9/3863

Abstract: A processor (210) includes a cache memory with a data storage unit (310) operating at a first clock frequency, and a tag unit and hit/miss logic operating at a second clock frequency different than the first clock frequency. The data storage unit (310) may advantageously be clocked faster than the tag unit and hit/miss logic, such as 2 times (2X) faster. This cache structure may advantageously be used as an L0 data cache in a microprocessor, especially in one which has plural execution core sections operating at the different clock frequencies. The processor (210) may utilise speculative data and has a "replay" function when the speculative data read from the cache turns out to be invalid.

Abstract translation: 处理器（210）包括具有以第一时钟频率工作的数据存储单元（310）的高速缓冲存储器，以及以与第一时钟频率不同的第二时钟频率工作的标签单元和命中/未命中逻辑。 有利地，数据存储单元（310）比标签单元更快地进行计时，并且更快地命中/错过逻辑，例如2倍（2X）。 这种高速缓存结构可以有利地用作微处理器中的L0数据高速缓存，特别是在具有在不同时钟频率下工作的多个执行核心部分的缓存结构中。 当从高速缓存读取的推测数据变得无效时，处理器（210）可以利用推测数据并具有“重放”功能。

公开(公告)号：WO1998019420A1

公开(公告)日：1998-05-07

申请号：PCT/US1997014442

申请日：1997-08-15

Applicant: INTEL CORPORATION

Inventor： INTEL CORPORATION ,  DAVIS, Derek, L.

IPC: H04L09/00

CPC classification number: G06F12/1408 ,  G06F21/72 ,  G06F21/85 ,  G06F2207/7219 ,  H04L9/0662 ,  H04L9/0822 ,  H04L9/0894 ,  H04L2209/12

Abstract: Circuitry implemented within a multi-chip module (200) comprising a first integrated circuit chip (205) and a second integrated circuit chip (210) coupled together through an interconnect (215). Both the first and second integrated circuit chips include a cryptographic engine (245, 235) coupled to the interconnect and a non-volatile memory element (250, 230) used to contain key information (240). These cryptographic engines are solely used to encrypt outgoing information being output across the interconnect or to decrypt incoming information received from the interconnect. This prevents fraudulent physical attack of information transmitted across the interconnect.

Abstract translation: 在多芯片模块（200）内实现的电路包括通过互连（215）耦合在一起的第一集成电路芯片（205）和第二集成电路芯片（210）。 第一和第二集成电路芯片都包括耦合到互连的密码引擎（245,235）和用于包含密钥信息（240）的非易失性存储元件（250,230）。 这些加密引擎仅用于加密跨互连输出的输出信息，或者解密从互连接收的传入信息。 这可以防止在互连上传输的信息的欺骗性物理攻击。

公开(公告)号：WO1998015130A1

公开(公告)日：1998-04-09

申请号：PCT/US1997016430

申请日：1997-09-15

Applicant: INTEL CORPORATION

Inventor： INTEL CORPORATION ,  NEEDHAM, Bradford, H.

IPC: H04N13/02

CPC classification number: G06T3/4038 ,  H04N5/23238 ,  H04N5/2624

Abstract: A process for producing a composite image from a plurality of images includes the following steps: a current image is selected from the plurality of images (312), the current image has an offset (314), a portion is extracted from the current image (316), the portion of the current image is then transferred onto a storage medium that stores the composite image (318), to a position corresponding to the offset (324).

Abstract translation: 用于从多个图像生成合成图像的处理包括以下步骤：从多个图像（312）中选择当前图像，当前图像具有偏移（314），从当前图像中提取部分（ 316），然后将当前图像的部分转移到存储合成图像（318）的存储介质上，到与偏移量相对应的位置（324）。

公开(公告)号：WO1998015086A1

公开(公告)日：1998-04-09

申请号：PCT/US1997013518

申请日：1997-07-30

Applicant: INTEL CORPORATION

Inventor： INTEL CORPORATION ,  DAVIS, Derek, L.

IPC: H04L09/32

CPC classification number: G06F12/1408 ,  G06F21/575 ,  G06F2211/1097

Abstract: A subsystem prevents unauthorized replacement of boot-up firmware (e.g., BIOS (63)) embedded in modifiable non-volatile memory devices (620) such as flash memory. The firmware device is contained in a secure boot device (54) which is responsive to the host processor (50). The security protection is established by the encryption and decryption of the boot-up instructions using a secret key (64) shared by both the secure boot device (54) and the host processor (50).

Abstract translation: 子系统防止非法更换嵌入在诸如闪存的可修改的非易失性存储器件（620）中的引导固件（例如，BIOS（63））。 固件设备包含在响应于主处理器（50）的安全引导设备（54）中。 通过使用由安全引导设备（54）和主处理器（50）共享的秘密密钥（64）对启动指令的加密和解密来建立安全保护。

公开(公告)号：WO1998010625A1

公开(公告)日：1998-03-12

申请号：PCT/US1997011170

申请日：1997-06-27

Applicant: INTEL CORPORATION

Inventor： INTEL CORPORATION ,  BANERJEE, Koushik ,  CHRONEOS, Robert, J., Jr. ,  MOZDZEN, Tom

IPC: H05K00/00

CPC classification number: H01L24/49 ,  H01L21/4846 ,  H01L23/49838 ,  H01L24/48 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/49109 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/30105 ,  H01L2924/3011 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2924/00012

Abstract: A method for plating an integrated circuit package (10). The method includes constructing a package (10) which has a plurality of internal bond fingers (40) that are subsequently coupled to an inegrated circuit (18). The package contains a plurality of vias that are electrically connected to the bond fingers (40). The vias (32) are also coupled to a layer of metallization (84) as a plating bar to plate the internal bond fingers (40). After plating, the metallization layer (84) is etched from the surface (16) of the package (10).

Abstract translation: 一种用于电镀集成电路封装（10）的方法。 该方法包括构造具有随后耦合到集成电路（18）的多个内部键合指（40）的封装（10）。 该封装包含电连接到接合指状物（40）的多个通孔。 通孔（32）还耦合到作为电镀条的金属化层（84），以平坦化内部粘结指状物（40）。 电镀后，从封装（10）的表面（16）蚀刻金属化层（84）。

公开(公告)号：WO1998010350A1

公开(公告)日：1998-03-12

申请号：PCT/US1997011419

申请日：1997-06-30

Applicant: INTEL CORPORATION

Inventor： INTEL CORPORATION ,  MACWILLIAMS, Peter, D. ,  SARANGDHAR, Nitin, V. ,  PAWLOWSKI, Stephen, S. ,  SINGH, Gurbir

IPC: G06F13/00

CPC classification number: G06F13/368 ,  G06F13/36 ,  G06F13/37 ,  G06F13/4213

Abstract: A data flow control mechanism (122) for a bus supporting two-and three-agent transactions includes a control logic (108) to place an indication of a request onto a computer system bus. The agent placing the indication on the bus then waits to place data corresponding to the request onto the bus until it has received an indication from another agent coupled to the bus that the other agent is ready to receive the data.

Abstract translation: 支持二代理和三代理事务的总线的数据流控制机制（122）包括一个控制逻辑（108），用于将请求的指示置于计算机系统总线上。 在总线上放置指示的代理然后等待将与该请求相对应的数据放置在总线上，直到其接收到来自与总线相连的其他代理程序的指示，即其他代理程序准备好接收数据。