公开(公告)号：US10229065B2

公开(公告)日：2019-03-12

申请号：US15396460

申请日：2016-12-31

Applicant: Intel Corporation

Inventor： Mohan J. Kumar ,  Murugasamy K. Nachimuthu

IPC: G06F3/06 ,  G06F12/1009

Abstract: Unified hardware and software two-level memory mechanisms and associated methods, systems, and software. Data is stored on near and far memory devices, wherein an access latency for a near memory device is less than an access latency for a far memory device. The near memory devices store data in data units having addresses in a near memory virtual address space, while the far memory devices store data in data units having addresses in a far memory address space, with a portion of the data being stored on both near and far memory devices. In response to memory read access requests, a determination is made to where data corresponding to the request is located on a near memory device, and if so the data is read from the near memory device; otherwise, the data is read from a far memory device. Memory access patterns are observed, and portions of far memory that are frequently accessed are copied to near memory to reduce access latency for subsequent accesses.

公开(公告)号：US20190065415A1

公开(公告)日：2019-02-28

申请号：US15916394

申请日：2018-03-09

Applicant: Intel Corporation

Inventor： Murugasamy K. Nachimuthu ,  Mohan J. Kumar ,  Mohamed Arafa ,  Suresh Chittor ,  Debendra Das Sharma ,  Pankaj Kumar

IPC: G06F13/16 ,  G06F3/06 ,  G06F13/42 ,  G06F12/0802

Abstract: Technologies for providing local disaggregation of memory include a compute sled. The compute sled includes a compute engine having a processor. The compute engine receives a request to perform a memory access operation on data residing in a first memory (e.g., a storage class memory) of the compute sled. The compute engine determines whether the data is cached in a second memory (e.g., a dynamic random-access memory (DRAM)). The compute engine performs, in response to a determination that the data is not cached in the second memory via a transactional protocol over a serial link connecting the processor and the first memory, the requested memory access operation.

公开(公告)号：US20190065172A1

公开(公告)日：2019-02-28

申请号：US15858748

申请日：2017-12-29

Applicant: Intel Corporation

Inventor： Murugasamy K. Nachimuthu ,  Mohan J. Kumar

IPC: G06F8/65 ,  H04L29/08 ,  H04L12/24

Abstract: Technologies for managing configuration-free platform firmware include a compute device, which further includes a management controller. The management controller is to receive a system configuration request to access a system configuration parameter of the compute device and access the system configuration parameter in response to a receipt of the system configuration request.

公开(公告)号：US10169268B2

公开(公告)日：2019-01-01

申请号：US15270151

申请日：2016-09-20

Applicant: Intel Corporation

Inventor： Mahesh Natu ,  Thanunathan Rangarajan ,  Gautam Doshi ,  Shamanna M. Datta ,  Baskaran Ganesan ,  Mohan J. Kumar ,  Rajesh S. Parthasarathy ,  Frank Binns ,  Rajesh Nagaraja Murthy ,  Robert C. Swanson

IPC: G06F9/46 ,  G06F9/30 ,  G11C7/10 ,  G11C11/406 ,  G06F13/24 ,  G06F9/38

Abstract: In one embodiment, the present invention includes a processor that has an on-die storage such as a static random access memory to store an architectural state of one or more threads that are swapped out of architectural state storage of the processor on entry to a system management mode (SMM). In this way communication of this state information to a system management memory can be avoided, reducing latency associated with entry into SMM. Embodiments may also enable the processor to update a status of executing agents that are either in a long instruction flow or in a system management interrupt (SMI) blocked state, in order to provide an indication to agents inside the SMM. Other embodiments are described and claimed.

公开(公告)号：US10110671B2

公开(公告)日：2018-10-23

申请号：US14961219

申请日：2015-12-07

Applicant: Intel Corporation

Inventor： Mrittika Ganguli ,  Mohan J. Kumar ,  Deepak S ,  Jaiber J. John

IPC: G06F15/173 ,  H04L29/08 ,  G06F9/50 ,  H04L12/24

Abstract: A method, system, and device for managing hardware resources in a cloud scheduling environment includes a zone controller. The zone controller can manage groups of node servers in a cloud datacenter using a checkin service. The checkin service allows server groups to be created automatically based on one or more hardware characteristics of the node servers, server health information, workload scheduling or facilities management parameters, and/or other criteria.

公开(公告)号：US20180262479A1

公开(公告)日：2018-09-13

申请号：US15976207

申请日：2018-05-10

Applicant: Intel Corporation

Inventor： Rajesh Poornachandran ,  Vincent J. Zimmer ,  Shahrok Shahidzadeh ,  Mohan J. Kumar ,  Sergiu D. Ghetie

IPC: H04L29/06 ,  G06F21/57 ,  G06F21/34

CPC classification number: H04L63/107 ,  G06F21/34 ,  G06F21/575 ,  G06F2221/2111

Abstract: Technologies for verifying authorized operation includes an administration server to query a dual-headed identification device of a server for identification data indicative of an identity of the server. The dual-headed identification device includes a wired communication circuit, a wireless communication circuit, and a memory having the identification data stored therein. The administration server further obtains the identification data from the dual-headed identification device of the server, determines a context of the server, and determines whether boot of the server is authorized based on the context of the server, the identification data of the server, and a security policy of the server.

公开(公告)号：US10025686B2

公开(公告)日：2018-07-17

申请号：US13663821

申请日：2012-10-30

Applicant: Intel Corporation

Inventor： Mrittika Ganguli ,  Tessil Thomas ,  Vinila Rose ,  Hussam Mousa ,  Mohan J. Kumar

IPC: G06F11/34

Abstract: In an embodiment, a processor includes a plurality of counters each to provide a count of a performance metric of at least one core of the processor, a plurality of threshold registers each to store a threshold value with respect to a corresponding one of the plurality of counters, and an event logic to generate an event digest packet including a plurality of indicators each to indicate whether an event occurred based on a corresponding threshold value and a corresponding count value. Other embodiments are described and claimed.

公开(公告)号：US10019354B2

公开(公告)日：2018-07-10

申请号：US14100721

申请日：2013-12-09

Applicant: Intel Corporation

Inventor： Sarathy Jayakumar ,  Mohan J. Kumar ,  Eswaramoorthi Nallusamy

IPC: G06F12/08 ,  G06F12/02 ,  G06F12/0868 ,  G06F12/0891 ,  G06F12/0866 ,  G06F12/0804

CPC classification number: G06F12/0246 ,  G06F12/0804 ,  G06F12/0866 ,  G06F12/0868 ,  G06F12/0891 ,  G06F2212/1032 ,  G06F2212/7203

Abstract: Apparatus, systems, and methods to manage memory operations are described. A cache controller is provided comprising logic to receive a transaction to operate on a data element in a cache memory, determine whether the data element is to be stored in a nonvolatile memory by querying a source address decoder (SAD), and, in response to a determination that the data element is to be stored in the nonvolatile memory, to forward the transaction to a memory controller coupled to the nonvolatile memory, and, in response to a determination that the data element is not to be stored in the nonvolatile memory, to drop the transaction from a cache flush procedure of the cache controller. Additionally, the cache controller may receive a confirmation signal from the memory controller that the data element was stored in the nonvolatile memory, and return a completion signal to an originator of the transaction. The cache controller may also include logic to place a processor core in a low power state.

公开(公告)号：US20180150372A1

公开(公告)日：2018-05-31

申请号：US15826051

申请日：2017-11-29

Applicant: Intel Corporation

Inventor： Murugasamy K. Nachimuthu ,  Mohan J. Kumar ,  Alberto J. Munoz

IPC: G06F11/30 ,  G06F3/06

CPC classification number: G06F3/0641 ,  G06F3/0604 ,  G06F3/0608 ,  G06F3/0611 ,  G06F3/0613 ,  G06F3/0617 ,  G06F3/0647 ,  G06F3/065 ,  G06F3/0653 ,  G06F3/067 ,  G06F7/06 ,  G06F8/65 ,  G06F8/654 ,  G06F8/656 ,  G06F8/658 ,  G06F9/3851 ,  G06F9/3891 ,  G06F9/4401 ,  G06F9/4881 ,  G06F9/5038 ,  G06F9/505 ,  G06F9/544 ,  G06F11/0709 ,  G06F11/0751 ,  G06F11/079 ,  G06F11/1453 ,  G06F11/3006 ,  G06F11/3034 ,  G06F11/3055 ,  G06F11/3409 ,  G06F12/023 ,  G06F12/0284 ,  G06F12/0692 ,  G06F13/1652 ,  G06F15/80 ,  G06F16/1744 ,  G06F21/57 ,  G06F21/6218 ,  G06F21/73 ,  G06F21/76 ,  G06F2212/401 ,  G06F2212/402 ,  G06F2221/2107 ,  G06T1/20 ,  G06T1/60 ,  G06T9/005 ,  H01R13/4538 ,  H01R13/631 ,  H03K19/1731 ,  H03M7/3084 ,  H03M7/40 ,  H03M7/42 ,  H03M7/60 ,  H03M7/6011 ,  H03M7/6017 ,  H03M7/6029 ,  H04L9/0822 ,  H04L12/2881 ,  H04L12/4633 ,  H04L41/044 ,  H04L41/046 ,  H04L41/0816 ,  H04L41/0853 ,  H04L41/0896 ,  H04L41/12 ,  H04L41/142 ,  H04L43/04 ,  H04L43/06 ,  H04L43/08 ,  H04L43/0894 ,  H04L47/20 ,  H04L47/2441 ,  H04L47/78 ,  H04L49/104 ,  H04L61/2007 ,  H04L63/1425 ,  H04L67/10 ,  H04L67/1014 ,  H04L67/327 ,  H04L67/36 ,  H05K7/1452 ,  H05K7/1487

Abstract: Technologies for generating manifest data for a sled include a sled to generate manifest data indicative of one or more characteristics of the sled (e.g., hardware resources, firmware resources, a configuration of the sled, or a health of sled components). The sled is also to associate an identifier with the manifest data. The identifier uniquely identifies the sled from other sleds. Additionally, the sled is to send the manifest data and the associated identifier to a server. The sled may also detect a change in the hardware resources, firmware resources, the configuration, or component health of the sled. The sled may also generate an update of the manifest data based on the detected change, where the update specifies the detected change in the hardware resources, firmware resources, the configuration, or component health of the sled. The sled may also send the update of the manifest data to the server.

公开(公告)号：US20180143923A1

公开(公告)日：2018-05-24

申请号：US15873089

申请日：2018-01-17

Applicant: Intel Corporation

Inventor： Mahesh Natu ,  Thanunathan Rangarajan ,  Gautam Doshi ,  Shamanna M. Datta ,  Baskaran Ganesan ,  Mohan J. Kumar ,  Rajesh S. Parthasarathy ,  Frank Binns ,  Rajesh Nagaraja Murthy ,  Robert C. Swanson

IPC: G06F13/24 ,  G11C11/406 ,  G11C7/10 ,  G06F9/46 ,  G06F9/30 ,  G06F9/38

CPC classification number: G06F13/24 ,  G06F9/30101 ,  G06F9/3017 ,  G06F9/30189 ,  G06F9/3851 ,  G06F9/461 ,  G11C7/1072 ,  G11C11/40615

Abstract: In one embodiment, the present invention includes a processor that has an on-die storage such as a static random access memory to store an architectural state of one or more threads that are swapped out of architectural state storage of the processor on entry to a system management mode (SMM). In this way communication of this state information to a system management memory can be avoided, reducing latency associated with entry into SMM. Embodiments may also enable the processor to update a status of executing agents that are either in a long instruction flow or in a system management interrupt (SMI) blocked state, in order to provide an indication to agents inside the SMM. Other embodiments are described and claimed.