公开(公告)号：US20230178658A1

公开(公告)日：2023-06-08

申请号：US17540560

申请日：2021-12-02

Applicant: Intel Corporation

Inventor： Prashant Majhi ,  Glenn Glass ,  Anand Murthy ,  Rushabh Shah

IPC: H01L29/786 ,  H01L29/06 ,  H01L29/423 ,  H01L21/02 ,  H01L29/66

CPC classification number: H01L29/78696 ,  H01L29/0665 ,  H01L29/42392 ,  H01L29/78618 ,  H01L21/0259 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/66742

Abstract: A semiconductor structure includes a body including semiconductor material, and a gate structure at least in part wrapped around the body. The semiconductor structure further includes a source region and a drain region, the body laterally extending between the source and drain regions. The body has a middle region between first and second tip regions. In an example, the source region at least in part wraps around the first tip region of the body, and/or the drain region at least in part wraps around the second tip region of the body. In another example, the body includes a core structure and a peripheral structure (e.g., cladding or layer that wraps around the core structure in the middle region of the body) that is compositionally different from the core structure. The body can be, for instance, a nanoribbon, nanosheet, or nanowire or a gate-all-around device or a forksheet device.

公开(公告)号：US20230163024A1

公开(公告)日：2023-05-25

申请号：US17530658

申请日：2021-11-19

Applicant: Intel Corporation

Inventor： Prashant Majhi ,  Anand Murthy

IPC: H01L21/768 ,  H01L23/532 ,  H01L23/522 ,  H01L23/528

CPC classification number: H01L21/76808 ,  H01L21/76877 ,  H01L23/53295 ,  H01L23/5226 ,  H01L23/5283 ,  H01L21/76846 ,  H01L21/76843 ,  H01L21/76873 ,  H01L2221/1036

Abstract: An integrated circuit structure includes a first interconnect layer including a first dielectric material. The first dielectric material has a first recess therein, the first recess having a first opening. The integrated circuit structure further includes a second interconnect layer above the first interconnect layer. The second interconnect layer includes a second dielectric material that has a second recess therein. The second recess has a second opening. In an example, at least a portion of the first opening of the first recess abuts and overlaps with at least a portion of the second opening of the second recess. In an example, a continuous conformal layer is on walls of the first and second recesses, and a continuous body of conductive material is within the first and second recesses.

公开(公告)号：US11640995B2

公开(公告)日：2023-05-02

申请号：US16616373

申请日：2017-06-20

Applicant: Intel Corporation

Inventor： Prashant Majhi ,  Brian S. Doyle ,  Kevin P. O'Brien ,  Abhishek A. Sharma ,  Elijah V. Karpov ,  Kaan Oguz

IPC: H01L29/78 ,  H01L27/24 ,  H01L29/06 ,  H01L29/51 ,  H01L21/28 ,  H01L27/22 ,  H01L29/423 ,  H01L29/49 ,  H01L29/66 ,  H01L29/786

Abstract: Ferroelectric field effect transistors (FeFETs) having band-engineered interface layers are described. In an example, an integrated circuit structure includes a semiconductor channel layer above a substrate. A metal oxide material is on the semiconductor channel layer, the metal oxide material having no net dipole. A ferroelectric oxide material is on the metal oxide material. A gate electrode is on the ferroelectric oxide material, the gate electrode having a first side and a second side opposite the first side. A first source/drain region is at the first side of the gate electrode, and a second source/drain region is at the second side of the gate electrode.

公开(公告)号：US11605671B2

公开(公告)日：2023-03-14

申请号：US17552546

申请日：2021-12-16

Applicant: Intel Corporation

Inventor： Prashant Majhi ,  Ravi Pillarisetty ,  Elijah V. Karpov ,  Brian S. Doyle ,  Abhishek A. Sharma

IPC: H01L27/24 ,  H01L27/22 ,  H01L45/00

Abstract: Embedded non-volatile memory structures having double selector elements are described. In an example, a memory device includes a word line. A double selector element is above the word line. The double selector element includes a first selector material layer, a second selector material layer different than the first selector material layer, and a conductive layer directly between the first selector material layer and the second selector material layer. A bipolar memory element is above the word line. A conductive electrode is between the double selector element and the bipolar memory element. A bit line is above the word line.

公开(公告)号：US11417705B2

公开(公告)日：2022-08-16

申请号：US16147555

申请日：2018-09-28

Applicant: Intel Corporation

Inventor： Brian Doyle ,  Prashant Majhi ,  Elijah Karpov ,  Ravi Pillarisetty ,  Ashishek Sharma

IPC: H01L27/24 ,  H01L45/00 ,  G11C13/00

Abstract: A memory cell is disclosed. The memory cell includes a word line contact, a cylindrical electrode having a top region and a bottom region, and RRAM material covering the surface of the cylindrical electrode from the top region to the bottom region. A select transistor contact is coupled to the bottom region of the cylindrical electrode.

公开(公告)号：US11289509B2

公开(公告)日：2022-03-29

申请号：US16640467

申请日：2017-09-29

Applicant: Intel Corporation

Inventor： Abhishek A. Sharma ,  Brian S. Doyle ,  Ravi Pillarisetty ,  Prashant Majhi ,  Elijah V. Karpov

IPC: H01L21/00 ,  H01L27/1159 ,  G11C11/22 ,  H01L29/51 ,  H01L29/78

Abstract: A ferroelectric field-effect transistor (FeFET) includes first and second gate electrodes, source and drain regions, a semiconductor region between and physically connecting the source and drain regions, a first gate dielectric between the semiconductor region and the first gate electrode, and a second gate dielectric between the semiconductor region and the second gate electrode. The first gate dielectric includes a ferroelectric dielectric. In an embodiment, a memory cell includes this FeFET, with the first gate electrode being electrically connected to a wordline and the drain region being electrically connected to a bitline. In another embodiment, a memory array includes wordlines extending in a first direction, bitlines extending in a second direction, and a plurality of such memory cells at crossing regions of the wordlines and the bitlines. In each memory cell, the wordline is a corresponding one of the wordlines and the bitline is a corresponding one of the bitlines.

公开(公告)号：US11250899B2

公开(公告)日：2022-02-15

申请号：US16633060

申请日：2017-09-29

Applicant: INTEL CORPORATION

Inventor： Abhishek A. Sharma ,  Brian S. Doyle ,  Ravi Pillarisetty ,  Prashant Majhi ,  Elijah V. Karpov

IPC: G11C11/22 ,  H01L27/11585

Abstract: A 1S-1T ferroelectric memory cell is provided that include a transistor and a two-terminal selector device. The transistor exhibits a low conductive state and a high conductive state (channel resistance), depending on drive voltage. The two-terminal selector device exhibits one of an ON-state and an OFF-state depending upon whether the transistor is in its low conductive state or its high conductive state. The transistor may be, for instance, a ferroelectric gate vertical transistor. Modulation of a polarization state of ferroelectric material of the vertical transistor may be utilized to switch the state of the selector device. The memory cell may thus selectively be operated in one of an ON-state and an OFF-state depending upon whether the selector device is in its ON-state or OFF-state.

公开(公告)号：US11233090B2

公开(公告)日：2022-01-25

申请号：US16632065

申请日：2017-09-27

Applicant: Intel Corporation

Inventor： Prashant Majhi ,  Ravi Pillarisetty ,  Elijah V. Karpov ,  Brian S. Doyle ,  Abhishek A. Sharma

IPC: H01L27/24 ,  H01L27/22 ,  H01L45/00

Abstract: Embedded non-volatile memory structures having double selector elements are described. In an example, a memory device includes a word line. A double selector element is above the word line. The double selector element includes a first selector material layer, a second selector material layer different than the first selector material layer, and a conductive layer directly between the first selector material layer and the second selector material layer. A bipolar memory element is above the word line. A conductive electrode is between the double selector element and the bipolar memory element. A bit line is above the word line.

公开(公告)号：US11195839B2

公开(公告)日：2021-12-07

申请号：US16635966

申请日：2017-09-29

Applicant: Intel Corporation

Inventor： Ravi Pillarisetty ,  Abhishek A. Sharma ,  Prashant Majhi ,  Elijah V. Karpov ,  Brian S. Doyle

IPC: H01L27/108 ,  G11C11/4096 ,  G11C14/00

Abstract: A memory device comprises a first selector and a storage capacitor in series with the first selector. A second selector is in parallel with the storage capacitor coupled between the first selector and zero volts. A plurality of memory devices form a 2S-1C cross-point DRAM array with 4F2 or less density.

公开(公告)号：US11171176B2

公开(公告)日：2021-11-09

申请号：US16634109

申请日：2017-09-27

Applicant: Intel Corporation

Inventor： Prashant Majhi ,  Abhishek A. Sharma ,  Elijah V. Karpov ,  Ravi Pillarisetty ,  Brian S. Doyle

IPC: H01L27/24 ,  H01L27/22 ,  H01L45/00

Abstract: Embedded non-volatile memory structures having asymmetric selector elements are described. In an example, a memory device includes a word line. An asymmetric selector element is above the word line. The asymmetric selector element includes a first electrode material layer, a selector material layer on the first electrode material layer, and a second electrode material layer on the selector material layer, the second electrode material layer different in composition than the first electrode material layer. A bipolar memory element is above the word line, the bipolar memory element on the asymmetric selector element. A bit line is above the word line.