公开(公告)号：US11188643B2

公开(公告)日：2021-11-30

申请号：US16234144

申请日：2018-12-27

Applicant: Intel Corporation

Inventor： Li Chen ,  Abhishek Basak ,  Salmin Sultana ,  Justin Gottschlich

IPC: G06F21/55 ,  G06N20/00 ,  G06N3/08 ,  G06F21/53

Abstract: Methods, apparatus, systems and articles of manufacture for detecting a side channel attack using hardware performance counters are disclosed. An example apparatus includes a hardware performance counter data organizer to collect a first value of a hardware performance counter at a first time and a second value of the hardware performance counter at a second time. A machine learning model processor is to apply a machine learning model to predict a third value corresponding to the second time. An error vector generator is to generate an error vector representing a difference between the second value and the third value. An error vector analyzer is to determine a probability of the error vector indicating an anomaly. An anomaly detection orchestrator is to, in response to the probability satisfying a threshold, cause the performance of a responsive action to mitigate the side channel anomaly.

公开(公告)号：US11188324B2

公开(公告)日：2021-11-30

申请号：US16725928

申请日：2019-12-23

Applicant: Intel Corporation

Inventor： Justin Gottschlich

IPC: G06F8/77 ,  G06F8/75 ,  G06F16/22

Abstract: Methods, apparatus, systems, and articles of manufacture to perform heterogeneous data structure selection via programmer annotations. An example apparatus includes a phase tracker to identify a first phase and a second phase, a cost predictor to estimate interaction costs of interacting with respective types of data structures within the first phase and the second phase, a tree constructor to construct a tree corresponding to a first data structure type, the tree including a first node in the first phase, a second node in the second phase, and an edge connecting the first node and the second node, the second node representing a second data structure type different from the first data structure type, a transformation cost calculator to calculate a transformation cost for the edge, and a branch selector to select a sequence of data structures based on the combined interaction costs and transformation costs.

公开(公告)号：US20210117807A1

公开(公告)日：2021-04-22

申请号：US17133168

申请日：2020-12-23

Applicant: Intel Corporation

Inventor： Shengtian Zhou ,  Fangke Ye ,  Roshni G. Iyer ,  Jesmin Jahan Tithi ,  Justin Gottschlich

IPC: G06N5/00 ,  G06N5/02 ,  G06K9/62 ,  G06F40/00

Abstract: Methods, apparatus, systems and articles of manufacture are disclosed to construct and compare program-derived semantic graphs comprising a leaf node creator to identify a first set of nodes within a parse tree, set a first abstraction level of a program-derived semantic graph (PSG) to contain the first set of nodes, an abstraction level determiner to access a second set of nodes, the second set of nodes to include the set of nodes in the PSG, create a third set of nodes, the third set of nodes to include the set of possible nodes at an abstraction level, determine whether the abstraction level is deterministic, a rule-based abstraction level creator to in response to determining the abstraction level is deterministic, construct the abstraction level, and a PSG comparator to access a first PSG and a second PSG, determine if the first PSG and the second PSG satisfy a similarity threshold.

公开(公告)号：US20210103434A1

公开(公告)日：2021-04-08

申请号：US17103477

申请日：2020-11-24

Applicant: Intel Corporation

Inventor： Anand Venkat ,  Justin Gottschlich ,  Shengtian Zhou ,  Vasileios Porpodas

IPC: G06F8/41 ,  G06F8/77 ,  G06F8/75 ,  G06F16/22

Abstract: An example apparatus comprises a transformation generator to generate a population of code variants corresponding to an input code, the population of code variants to include transformation sequences of the input code, a dependence analyzer to analyze the population of code variants for dependence vectors, a profile controller to profile the population of code variants to determine performance metrics of hardware during an execution of respective ones of the transformation sequences, and a hash code generator to generate hash codes for storing in a database, the hash codes (a) corresponding to a combination of the dependence vectors and respective performance metrics and (b) mapped to respective transformation sequences.

公开(公告)号：US10908884B2

公开(公告)日：2021-02-02

申请号：US16455379

申请日：2019-06-27

Applicant: Intel Corporation

Inventor： Adam Herr ,  Derek Gerstmann ,  Justin Gottschlich ,  Mikael Bourges-Sevenier ,  Sridhar Sharma

IPC: G06F9/44 ,  G06F8/41 ,  G06N3/08 ,  G06F8/54 ,  G06F9/48

Abstract: Methods, apparatus, systems and articles of manufacture are disclosed for runtime scheduling of software executing on a heterogeneous system. An example apparatus includes in response to a variant compiler to generate a representation of an algorithm in a domain-specific language (DSL), a compilation auto-scheduler to generate a schedule based on configurations for processing elements of the heterogeneous system, the processing elements including at least a first and a second processing element, the variant compiler to compile variant binaries based on the schedule, each of the variant binaries associated with the algorithm in the DSL, the variant binaries including a first variant binary corresponding to the first processing element and a second variant binary corresponding to the second processing element, and an application compiler to generate a fat binary including a runtime scheduler to select one or more of the variant binaries to execute a workload based on the schedule.

公开(公告)号：US10853554B2

公开(公告)日：2020-12-01

申请号：US16456825

申请日：2019-06-28

Applicant: Intel Corporation

Inventor： Javier Sebastian Turek ,  Javier Felip Leon ,  Alexander Heinecke ,  Evangelos Georganas ,  Luis Carlos Maria Remis ,  Ignacio Javier Alvarez ,  David Israel Gonzalez Aguirre ,  Shengtian Zhou ,  Justin Gottschlich

IPC: G06F30/30 ,  G06F30/398 ,  G06N3/04 ,  G06N3/08

Abstract: Systems and methods for determining a configuration for a microarchitecture are described herein. An example system includes a proposal generator to generate a first candidate configuration of parameters for the microarchitecture, a machine learning model to process the first candidate configuration of parameters to output estimated performance indicators for the microarchitecture, an uncertainty checker to determine whether the estimated performance indicators are reliable, and a performance checker. In response to a determination that the estimated performance indicators are reliable, the performance checker is to determine whether the estimated performance indicators have improved toward a target. Further, if the estimated performance indicators have improved, the performance checker is to store the first candidate configuration of parameters in a memory as a potential solution for a microarchitecture without performing a full simulation on the first candidate configuration of parameters.

公开(公告)号：US20190325314A1

公开(公告)日：2019-10-24

申请号：US16456863

申请日：2019-06-28

Applicant: Intel Corporation

Inventor： Mikael Bourges-Sevenier ,  Adam Herr ,  Sridhar Sharma ,  Derek Gerstmann ,  Todd Anderson ,  Justin Gottschlich

IPC: G06N3/08 ,  G06F17/16

Abstract: Methods, apparatus, systems and articles of manufacture to optimize execution of a machine learning model are disclosed. An example apparatus includes a quantizer to quantize a layer of a model based on an execution constraint, the layer of the model represented by a matrix. A packer is to pack the quantized layer of the matrix to create a packed layer represented by a packed matrix, the packed matrix having non-zero values of the matrix grouped together along at least one of a row or a column of the matrix. A blocker is to block the packed layer into a blocked layer by dividing the non-zero values in the packed matrix into blocks. A fuser is to fuse the blocked layer into a pipeline. A packager is to package the pipeline into a binary.

公开(公告)号：US20190324727A1

公开(公告)日：2019-10-24

申请号：US16455358

申请日：2019-06-27

Applicant: Intel Corporation

Inventor： Marcos Carranza ,  Mats Agerstam ,  Justin Gottschlich ,  Alexander Heinecke ,  Cesar Martinez-Spessot ,  Maria Ramirez Loaiza ,  Mohammad Mejbah Ul Alam ,  Shengtian Zhou

IPC: G06F8/33 ,  G06F8/41

Abstract: Methods, apparatus, systems and articles of manufacture are disclosed for code review assistance for dynamically typed languages. An example apparatus to analyze a segment of code includes a function identifier to identify a first input of a first function call included in the segment of the code, a parameter type vector (PTV) estimatior model to estimate a first data structure based on the first input, the PTV estimatior model generated via a set of reviewed code, a PTV determiner to generate a second data structure based on a data parameter type of the first input, an error comparator to determine a first reconstruction error based on the first data structure, and the second data structure and a recommendation generator to, if the first reconstruction error does not satisfy a recommendation threshold, generate a first recommendation to review the first function call.

公开(公告)号：US20190317740A1

公开(公告)日：2019-10-17

申请号：US16455379

申请日：2019-06-27

Applicant: Intel Corporation

Inventor： Adam Herr ,  Derek Gerstmann ,  Justin Gottschlich ,  Mikael Bourges-Sevenier ,  Sridhar Sharma

IPC: G06F8/41 ,  G06F8/54 ,  G06N3/08

Abstract: Methods, apparatus, systems and articles of manufacture are disclosed for runtime scheduling of software executing on a heterogeneous system. An example apparatus includes in response to a variant compiler to generate a representation of an algorithm in a domain-specific language (DSL), a compilation auto-scheduler to generate a schedule based on configurations for processing elements of the heterogeneous system, the processing elements including at least a first and a second processing element, the variant compiler to compile variant binaries based on the schedule, each of the variant binaries associated with the algorithm in the DSL, the variant binaries including a first variant binary corresponding to the first processing element and a second variant binary corresponding to the second processing element, and an application compiler to generate a fat binary including a runtime scheduler to select one or more of the variant binaries to execute a workload based on the schedule.

公开(公告)号：US20190314984A1

公开(公告)日：2019-10-17

申请号：US16455190

申请日：2019-06-27

Applicant: Intel Corporation

Inventor： David I. Gonzalez Aguirre ,  Javier Felip Leon ,  Javier Sebastián Turek ,  Luis Carlos Maria Remis ,  Ignacio Javier Alvarez ,  Justin Gottschlich

IPC: B25J9/16

Abstract: Apparatus, systems, methods, and articles of manufacture for automatic robot perception programming by imitation learning are disclosed. An example apparatus includes a percept mapper to identify a first percept and a second percept from data gathered from a demonstration of a task and an entropy encoder to calculate a first saliency of the first percept and a second saliency of the second percept. The example apparatus also includes a trajectory mapper to map a trajectory based on the first percept and the second percept, the first percept skewed based on the first saliency, the second percept skewed based on the second saliency. In addition, the example apparatus includes a probabilistic encoder to determine a plurality of variations of the trajectory and create a collection of trajectories including the trajectory and the variations of the trajectory. The example apparatus also includes an assemble network to imitate an action based on a first simulated signal from a first neural network of a first modality and a second simulated signal from a second neural network of a second modality, the action representative of a perceptual skill.