公开(公告)号：JPH0637710A

公开(公告)日：1994-02-10

申请号：JP19123092

申请日：1992-07-20

Applicant: NEC CORP

Inventor： ICHIYOSHI OSAMU

IPC: H04B1/50 ,  H04B7/212 ,  H04B7/26

Abstract: PURPOSE:To realize a mobile a mobile body satellite communication system without the need of a branching filter used for a conventional system in which two-way digital communication is served among lots of mobile stations and a few base stations by means of the FDM system. CONSTITUTION:In the case of two-way digital communication from a base station to plural mobile stations by using different transmission reception frequencies, the system is featured such that a first half time slot field in one frame synchronously with a unique word of a digital signal sent from the base station to the mobile stations is used for a time slot field of a reception signal of the mobile stations and a latter half time slot field in the one frame of the digital signal is used for a time slot field of a transmission signal of the mobile stations, and is provided with a changeover control circuit 14 which uses a frame synchronizing separator circuit 10 provided to a reception section of each mobile station detecting a frame synchronizing signal from the unique word, sets the first half time slot field and the latter half time slot field based on the frame synchronizing signal to output control signal, with a 1st RF switch 2 turning on/off a high power transmission signal of a transmission section with the control signal of the changeover control circuit 14 and with a 2nd RF switch 3 turning on/off a reception signal of a low noise amplifier of the reception section.

公开(公告)号：JPH05122066A

公开(公告)日：1993-05-18

申请号：JP30654691

申请日：1991-10-26

Applicant: NEC CORP

Inventor： ICHIYOSHI OSAMU

IPC: H03L7/10 ,  H03L7/185 ,  H03L7/197

Abstract: PURPOSE:To obtain the frequency signals of fine frequency steps over a wide frequency range and also to obtain a frequency synthesizer where phase noise is suppressed. CONSTITUTION:The frequency synthesizer is constituted of a reference oscillator 1, DDS(direct-digital synthesizer) 2 generating the frequency signal which is designated by a channel number, a frequency multiplying circuit 3 multiplying the output of DDS 2, a variable frequency multiplying circuit 4 multiplying the output of the reference oscillator 1, VCO(voltage control oscillator) 8, a frequency-divider 9 frequency-dividing the output of VCO, a mixer 5 obtaining frequency difference between the output of the frequency-divider 9 and the output of the variable frequency multiplying circuit 4, LPF 10, a phase comparator 6 phase-comparing the output of OPF 10 with the output of the frequency multiplying circuit 3 and a loop filter 7 smoothing the output.

公开(公告)号：JPH0590960A

公开(公告)日：1993-04-09

申请号：JP25073891

申请日：1991-09-30

Applicant: NEC CORP

Inventor： ICHIYOSHI OSAMU

IPC: H03L7/10 ,  H03L7/06 ,  H03L7/22

Abstract: PURPOSE:To provide a narrow band PLL circuit operated under a low C/N condition by providing L the PLL circuit implementing correct synchronization locking even with an initial frequency error. CONSTITUTION:The circuit is provided with a limiter 5 receiving a complex sample string signal including a complex sinusoidal wave signal and limiting the amplitude to a constant value, a complex multiplier 10 receiving an output signal of the limiter 5 and applying complex multiplication between the signal with a conjugate value of the complex sample string output signal from an auxiliary terminal, a loop filter 11 filtering an output signal of the complex multiplier 10, a delay device 13 delaying one sample of the complex sample signal, a complex multiplier 12 applying complex multiplication to an output signal of the delay device and a loop filter output signal, and a limiter 6 receiving an output signal of the complex multiplier 12 to limit the amplitude to a constant value, inputting the result to the delay device 12 as an output signal of the phase locked loop circuit and feeding back the output signal to the auxiliary terminal of the complex multiplier 10.

公开(公告)号：JPH0575662A

公开(公告)日：1993-03-26

申请号：JP23264391

申请日：1991-09-12

Applicant: NEC CORP

Inventor： ICHIYOSHI OSAMU

IPC: H04L27/38 ,  H04L27/22

Abstract: PURPOSE:To execute correct acquisition of synchronism even when an initial frequency error is large by utilizing the frequency discrimination action so as to suppress a frequency error through the automatic frequency control. CONSTITUTION:When a frequency error is large at the time of the acquisition and even if the phase error detection of a complex multiplier 9 is not worked well, a frequency discrimination signal is obtained by a output signal of a complex multiplier 14. The frequency discrimination signal is sent to an integration device 11 via an adder 16 and a loop filter 10, the integration device 11 and a cosine/sine value generator 12 act as a numerical control oscillator and the automatic frequency control is implemented in a direction to decrease the frequency error. When the frequency error is decreased, the phase error detection by the complex multiplier 9 is started to operate the phase locked loop. When a frequency of a reception signal is changed during the operation, a frequency discrimination signal appears again at an output of the complex multiplier 14, the automatic frequency control is operated to reduce the frequency error thereby establishing the loop synchronization state again.

公开(公告)号：JPH04196620A

公开(公告)日：1992-07-16

申请号：JP31800590

申请日：1990-11-26

Applicant: NEC CORP

Inventor： ICHIYOSHI OSAMU

IPC: H03L7/197

Abstract: PURPOSE:To reduce phase noise even with respect to a small step size by implementing phase lock operation in a phase locked loop at a frequency higher than a step frequency. CONSTITUTION:A reference oscillator 1 generates a reference frequency signal having a reference frequency being a multiple of (MXm) of a step frequency f, a frequency divider 21 applies 1/M frequency division to the reference frequency signal to output a signal of a frequency m f. A frequency divider 6 applies 1/N frequency division to an output frequency f0 of a voltage controlled oscillator 5 and its output signal is frequency-multiplied by an m-multiple circuit 7 and a signal of frequency mf0/N. The phase of the signal is compared with a phase of the signal m f from the frequency divider 21 at a phase comparator 3. Thus, the phase locking by the phase comparator 3 is implemented at a frequency m f being a multiple of (m) of the step frequency f. Thus, the band width of the phase locked loop is expanded by a multiple of (m) and phase noise of the voltage controlled oscillator 5 is suppressed by the expansion.

公开(公告)号：JPH04144441A

公开(公告)日：1992-05-18

申请号：JP26660890

申请日：1990-10-05

Applicant: NEC CORP

Inventor： ICHIYOSHI OSAMU

IPC: H03L7/08 ,  H03L7/099 ,  H03L7/16 ,  H04L7/00 ,  H04L25/05

Abstract: PURPOSE:To increase a pull-in speed by finding out a difference between the 1st and 2nd modulo multiplication signal and using the difference signal as a control signal. CONSTITUTION:A digital phase synchronizing loop is constituted of a modulo 2Rn multiplier 14, an adder 15, an LPF 16, an NCO 17, and a modulo 2Rm multiplier 18, and in a synchronous state, nf1=mf2 (mod2R) is attained. Provided that f1 and f2 are the 1st and 2nd frequency values, and since the f2 is set up to a nominal frequency value by M (fixed information), nf1=mf2 is formed so that f2=(n/m)f1 is formed and an objective frequency signal is obtained. Even if the values (m), (n) are large, speed conversion having a conversion ratio n/m can be attained without reducing the equivalent band width of a PLL and the pull-in speed can be increased.

公开(公告)号：JPH0362644A

公开(公告)日：1991-03-18

申请号：JP19822589

申请日：1989-07-31

Applicant: NEC CORP ,  NIPPON ELECTRIC ENG

Inventor： ICHIYOSHI OSAMU ,  TANAKA SHINICHI

IPC: H04L1/00

Abstract: PURPOSE:To reduce bit error noise by branching a digitized voice signal into high-order and low-order at a sender side, encoding them, outputting the result of synthesis, separating it into 1st and 2nd components at a receiver side, applying error correction decoding and synthesizing them. CONSTITUTION:A voice coder 1 at a sender side applies voice coding to a voice while M-bit is used as one word, inputs the signal to a branch circuit 2, where the signal is branched into high-order N1-bit and low-order N2-bit. The high-order N1-bit is inputted to a coder 3 to apply coding aiming at high gain error correction coding in a coding rate of 1:m to the high-order N1-bit. Similarly, the low-order N2-bit is inputted to a coder 4 to apply coding aiming at high gain error correction coding in a coding rate of 1:n to the low-order N2-bit. Outputs of them are synthesized at a synthesis circuit 7. A demultiplex circuit 10 at a receiver side demultiplexes the signal into components 1, 2, they are subject to error correction decoding at error correction decoders 11, 12 and the result of decoding is synthesized by a synthesis circuit 13. The output of the circuit 13 is subject to voice decoding by a voice decoder 14 to obtain a voice signal in which the bit error rate of the high-order N1-bit is remarkably decreased more than a conventional system.

公开(公告)号：JPH02230846A

公开(公告)日：1990-09-13

申请号：JP5128589

申请日：1989-03-03

Applicant: NEC CORP

Inventor： ICHIYOSHI OSAMU

IPC: H04L27/22

Abstract: PURPOSE:To prevent the effect of phase noise by providing a delay circuit in parallel with a carrier regenerating circuit and retarding a PSK signal inputted to a multiplier by a signal delay in the carrier regenerating circuit. CONSTITUTION:A delay circuit 2 gives a delay nearly equal to a signal delay in a carrier regenerating circuit 1 to an input PSK signal and supplies the result to other input terminal of a multiplier 3. That is, the PSK signal inputted to the multiplier 3 is retarded by a signal delay in the carrier regenerating circuit 1. As a result, let a signal delay in the carrier regenerating circuit 1 be tau and the delay in the delay circuit 2 be tau', then phase jitter theta2J in the multiplier 3 caused by phase noise is expressed as beta(tau-tau')+gamma(tau-tau') . That is, when a difference between tau and tau' is decreased, the phase jitter can be decreased. Thus, the effect of the phase noise is much decreased.

公开(公告)号：JPH02212930A

公开(公告)日：1990-08-24

申请号：JP3262189

申请日：1989-02-14

Applicant: NEC CORP ,  NIPPON ELECTRIC ENG

Inventor： ICHIYOSHI OSAMU ,  TANAKA SHINICHI

IPC: G06F1/02 ,  G06F7/544 ,  G06F17/10

Abstract: PURPOSE:To realize a voltage controlled oscillator of extremely low modulating sensitivity by executing a prescribed processing with the use of a digital signal processor (DSP), and executing the processing for fluctuation at interrupting timing. CONSTITUTION:A voltage controlled oscillator (VCO) consists of a DSP 10 operated at high-speed clocks. The DSP 10 reads a binary control signal 100 supplied from the outside by an interrupting signal 120 applied from the outside, executes the arithmetic processing according to a built-in processing procedure, and a processing result is outputted from parallel ports 11 to 18 in a parallel binary format. Further the highest-order bit of the parallel binary is used as the interrupting signal 120 as well. Thus the digital VCO at the extremely low modulating sensitivity can be realized.

公开(公告)号：JPH01319319A

公开(公告)日：1989-12-25

申请号：JP15123588

申请日：1988-06-21

Applicant: NEC CORP

Inventor： ICHIYOSHI OSAMU ,  KAWAUCHI TORU

IPC: H03H17/02

Abstract: PURPOSE:To select the transmission frequency band width and the frequency characteristic freely by using the 2nd high speed Fourier transformation device and the 2nd polyphase digital filter group so as to convert an input signal again into an analog signal. CONSTITUTION:After an input signal is converted at first into a digital signal by an A/D converter 4 in an FDM branch circuit 1, the signal is demultiplexed into N-set of frequency components by N-phase digital fiters(PDF) 5-1-5-N and the 1st high speed Fourier transformation device (FET) 6. The required component among N-set of frequency components, that is, the component desired to be transmitted is selected by a switch circuit 2. The signal from the switch circuit 2 is integrated into one carrier by the 2nd high speed Fourier transformation device (FET) 7 having the opposite function to the process of the FDM demultiplexing circuit 1 and the N-phase digital filters (PDF) 8-1-8-N in a group modulator 3 and D-A converted by a D/A converter 9. Thus, only a component of the frequency band selected by the switching circuit 2 is passed through.