公开(公告)号：US10714583B2

公开(公告)日：2020-07-14

申请号：US16037095

申请日：2018-07-17

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Christian Rivero ,  Guilhem Bouton ,  Pascal Fornara ,  Julien Delalleau

IPC: H01L29/423 ,  H01L29/49 ,  H01L29/78 ,  H01L29/06 ,  H01L29/08 ,  H01L21/28 ,  H01L21/8234

Abstract: A MOS transistor is produced on and in an active zone which includes a source region and a drain region. The active zone is surrounded by an insulating region. A conductive gate region of the transistor has two flanks which extend transversely to a source-drain direction, and the conductive gate region overlaps two opposite edges of the active zone act overlap zones. The conductive gate region includes, at a location of at least one overlap zone, at least one conductive tag which projects from at least one flank at a foot of the conductive gate region. The conductive tag covers a part of the active zone and a part of the insulating region.

公开(公告)号：US10600737B2

公开(公告)日：2020-03-24

申请号：US15722703

申请日：2017-10-02

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Christian Rivero ,  Pascal Fornara ,  Jean-Philippe Escales

IPC: H01L21/31 ,  H01L23/532 ,  H01L21/768 ,  H01L21/02 ,  H01L23/522 ,  H01L23/528

Abstract: A non-porous dielectric barrier is provided between a porous portion of a dielectric region and an electrically conductive element of an interconnect portion of an integrated circuit. This non-porous dielectric barrier protects the integrated circuit from breakdown of the least one dielectric region caused by electrical conduction assisted by the presence of defects located in the at least one dielectric region.

公开(公告)号：US20190295965A1

公开(公告)日：2019-09-26

申请号：US16358223

申请日：2019-03-19

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Pascal Fornara

IPC: H01L23/62 ,  H01L23/525 ,  H01H85/02

Abstract: A semiconductor wafer includes first zones containing integrated circuits, each first zone including a substrate and a sealing ring at a periphery of the substrate. The first zones are separated from each other by second zones defining cutting lines or paths. The integrated circuit includes an electrically conductive fuse that extends between a first location inside the integrated circuit and a second location situated outside the integrated circuit beyond one of the cutting lines. This electrically conductive fuse includes a portion that passes through the sealing ring and another portion that straddles the adjacent cutting line. The portion of the fuse that passes through is electrically isolated from the sealing ring and from the substrate. The straddling portion is configured to be sliced, when cutting the wafer along the cutting line, so as to cause the fuse to change from an electrical on state to an electrical off state.

公开(公告)号：US10379254B2

公开(公告)日：2019-08-13

申请号：US14985037

申请日：2015-12-30

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Abderrezak Marzaki ,  Yoann Goasduff ,  Virginie Bidal ,  Pascal Fornara

IPC: H01H9/02 ,  H01H37/42 ,  H01H61/013 ,  G01V7/04 ,  B81B3/00 ,  B81C1/00 ,  H01L49/02 ,  H01H37/04 ,  H01H37/32 ,  H01L21/3213 ,  H01L29/423

Abstract: A method for producing an integrated circuit pointed element is disclosed. An element has a projection with a concave part directing its concavity towards the element. The element includes a first etchable material. A zone is formed around the concave part of the element. The zone includes a second material that is less rapidly etchable than the first material for a particular etchant. The first material and the second material are etched with the particular etchant to form an open crater in the concave part and thus to form a pointed region of the element.

公开(公告)号：US20190172785A1

公开(公告)日：2019-06-06

申请号：US16270356

申请日：2019-02-07

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Pascal Fornara ,  Christian Rivero

IPC: H01L23/525 ,  H01L21/768 ,  H01L23/522

Abstract: An integrated circuit includes a substrate; an interconnect portion disposed over the substrate, the interconnect portion comprising multiple metallization levels separated by an insulating region; and an antifuse structure coated with a portion of the insulating region, the antifuse structure comprising a beam held at two different points by two arms, a body, and an antifuse insulating zone, the beam, the body and the arms being metal and located within a same metallization level, the body and the beam mutually making contact via the antifuse insulating zone, the antifuse insulating zone configured to undergo breakdown in the presence of a breakdown potential difference between the body and the beam.

公开(公告)号：US10242944B2

公开(公告)日：2019-03-26

申请号：US15610323

申请日：2017-05-31

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Pascal Fornara ,  Christian Rivero

IPC: H01L23/525 ,  H01L21/768 ,  H01L23/522

Abstract: An integrated circuit includes a substrate; an interconnect portion disposed over the substrate, the interconnect portion comprising multiple metallization levels separated by an insulating region; and an antifuse structure coated with a portion of the insulating region, the antifuse structure comprising a beam held at two different points by two arms, a body, and an antifuse insulating zone, the beam, the body and the arms being metal and located within a same metallization level, the body and the beam mutually making contact via the antifuse insulating zone, the antifuse insulating zone configured to undergo breakdown in the presence of a breakdown potential difference between the body and the beam.

公开(公告)号：US10211291B2

公开(公告)日：2019-02-19

申请号：US15864451

申请日：2018-01-08

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Guilhem Bouton ,  Pascal Fornara ,  Christian Rivero

IPC: H01L29/10 ,  H01L29/78 ,  H01L29/06 ,  H01L21/762 ,  H01L21/763 ,  H01L27/112

Abstract: An integrated circuit includes a substrate and at least one component unfavorably sensitive to compressive stress which is arranged at least partially within an active region of the substrate limited by an insulating region. To address compressive stress in the active region, the circuit further includes at least one electrically inactive trench located at least in the insulating region and containing an internal area configured to reduce compressive stress in the active region. The internal area is filled with polysilicon. The polysilicon filled trench may further extend through the insulating region and into the substrate.

公开(公告)号：US10177101B2

公开(公告)日：2019-01-08

申请号：US15596767

申请日：2017-05-16

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Christian Rivero ,  Pascal Fornara ,  Guilhem Bouton ,  Mathieu Lisart

IPC: H01L23/00 ,  H01L21/311 ,  H01L23/528 ,  H01L27/088 ,  H01L23/522 ,  H01L23/58 ,  H01L21/768

Abstract: An integrated circuit includes a semiconductor substrate and a multitude of electrically conductive pads situated between component zones of the semiconductor substrate and a first metallization level of the integrated circuit, respectively. The multitude of electrically conductive pads are encapsulated in an insulating region and include: first pads, in electrical contact with corresponding first component zones, and at least one second pad, not in electrical contact with a corresponding second component zone.

公开(公告)号：US10026563B2

公开(公告)日：2018-07-17

申请号：US14289784

申请日：2014-05-29

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Antonio Di-Giacomo ,  Christian Rivero ,  Pascal Fornara

IPC: H01H1/00 ,  H01H61/00 ,  H01H37/00

Abstract: An integrated circuit, comprising an electrical-switching mechanical device in a housing having at least one first thermally deformable assembly including a beam held in at least two different locations by at least two arms secured to edges of the housing, the beam and the arms being metallic and situated within the same first metallization level and an electrically conductive body, wherein the said first thermally deformable assembly has at least one first configuration at a first temperature and a second configuration when at least one is at a second temperature different from the first temperature, wherein the beam is at a distance from the body in the first configuration and in contact with the said body and immobilized by the said body in the second configuration and establishing or prohibiting an electrical link passing through the body and through the beam.

公开(公告)号：US09916902B2

公开(公告)日：2018-03-13

申请号：US15218261

申请日：2016-07-25

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Pascal Fornara ,  Christian Rivero

IPC: H01L23/00 ,  H01L27/115 ,  H01L21/82 ,  H01L29/78 ,  G11C16/22 ,  H01L21/311 ,  H01L21/8238 ,  H01L21/8234 ,  H01L21/74 ,  H01L21/66

CPC classification number: G11C16/22 ,  G06F21/87 ,  H01L21/31116 ,  H01L21/74 ,  H01L21/823481 ,  H01L21/823892 ,  H01L22/14 ,  H01L22/34 ,  H01L23/57 ,  H01L23/576 ,  H01L27/115 ,  H01L29/7846

Abstract: The thinning of a semiconductor substrate of an integrated circuit from a back face is detected using the measurement of a physical quantity representative of the resistance between the ends of two electrically-conducting contacts situated at an interface between an insulating region and an underlying substrate region. The two electrically-conducting contacts extend through the insulating region to reach the underlying substrate region.