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    Semiconductor device with multiple space-charge control electrodes
    81.
    发明授权
    Semiconductor device with multiple space-charge control electrodes 有权
    具有多个空间电荷控制电极的半导体器件

    公开(公告)号：US09256240B2

    公开(公告)日：2016-02-09

    申请号：US14527203

    申请日：2014-10-29

    Applicant: Sensor Electronic Technology, Inc.

    Inventor： Grigory Simin ,  Michael Shur ,  Remigijus Gaska

    IPC: H01L29/02 ,  G05F3/02 ,  H01L29/20 ,  H01L29/40

    CPC classification number: G05F3/02 ,  H01L29/2003 ,  H01L29/402 ,  H01L29/404 ,  H01L29/42316 ,  H01L29/4232 ,  H01L29/7786 ,  H01L29/872

    Abstract: A circuit including a semiconductor device having a set of space-charge control electrodes is provided. The set of space-charge control electrodes is located between a first terminal, such as a gate or a cathode, and a second terminal, such as a drain or an anode, of the device. The circuit includes a biasing network, which supplies an individual bias voltage to each of the set of space-charge control electrodes. The bias voltage for each space-charge control electrode can be: selected based on the bias voltages of each of the terminals and a location of the space-charge control electrode relative to the terminals and/or configured to deplete a region of the channel under the corresponding space-charge control electrode at an operating voltage applied to the second terminal.

    Abstract translation: 提供了包括具有一组空间电荷控制电极的半导体器件的电路。 该组空间电荷控制电极位于该器件的第一端子（例如栅极或阴极）和第二端子（例如漏极或阳极）之间。 电路包括偏置网络，其向每组空间电荷控制电极中的每一个提供单独的偏置电压。 每个空间电荷控制电极的偏置电压可以是：基于每个端子的偏置电压和空间电荷控制电极相对于端子的位置来选择和/或被配置为消耗通道下方的区域 对应的空间电荷控制电极施加到第二端子的工作电压。

    Semiconductor Device with Low-Conducting Buried and/or Surface Layers
    84.
    发明申请
    Semiconductor Device with Low-Conducting Buried and/or Surface Layers 有权
    具有低导电埋地和/或表面层的半导体器件

    公开(公告)号：US20150102364A1

    公开(公告)日：2015-04-16

    申请号：US14576303

    申请日：2014-12-19

    Applicant: SENSOR ELECTRONIC TECHNOLOGY, INC.

    Inventor： Grigory Simin ,  Michael Shur ,  Remigijus Gaska

    IPC: H01L23/552 ,  H01L29/205 ,  H01L29/165 ,  H01L29/267 ,  H01L29/778 ,  H01L29/16

    CPC classification number: H01L29/205 ,  G06F17/5068 ,  H01L29/1075 ,  H01L29/1079 ,  H01L29/2003 ,  H01L29/408 ,  H01L29/7786

    Abstract: A device including one or more low-conducting layers is provided. A low-conducting layer can be located below the channel and one or more attributes of the low-conducting layer can be configured based on a minimum target operating frequency of the device and a charge-discharge time of a trapped charge targeted for removal by the low-conducting layer or a maximum interfering frequency targeted for suppression using the low-conducting layer. For example, a product of the lateral resistance and a capacitance between the low-conducting layer and the channel can be configured to be larger than an inverse of the minimum target operating frequency and the product can be smaller than at least one of: the charge-discharge time or an inverse of the maximum interfering frequency.

    Abstract translation: 提供了包括一个或多个低导电层的器件。 低导电层可以位于通道下方，并且可以基于器件的最小目标工作频率和针对要被除去的俘获电荷的充电 - 放电时间来配置低导电层的一个或多个属性 低导电层或使用低导电层抑制的最大干扰频率。 例如，横向电阻和低导电层和沟道之间的电容的乘积可以被配置为大于最小目标工作频率的倒数，并且乘积可以小于以下中的至少一个：电荷 - 充电时间或最大干扰频率的倒数。

    Semiconductor device with low-conducting buried and/or surface layers
    85.
    发明授权
    Semiconductor device with low-conducting buried and/or surface layers 有权
    具有低导电掩埋和/或表面层的半导体器件

    公开(公告)号：US08994035B2

    公开(公告)日：2015-03-31

    申请号：US13682139

    申请日：2012-11-20

    Applicant: Sensor Electronic Technology, Inc.

    Inventor： Grigory Simin ,  Michael Shur ,  Remigijus Gaska

    IPC: H01L29/78 ,  H01L29/16 ,  G06F17/50 ,  H01L29/40 ,  H01L29/423 ,  H01L29/778 ,  H01L29/10 ,  H01L29/20

    CPC classification number: H01L29/78 ,  G06F17/5068 ,  H01L29/1075 ,  H01L29/1079 ,  H01L29/1608 ,  H01L29/2003 ,  H01L29/408 ,  H01L29/423 ,  H01L29/7786

    Abstract: A device including one or more low-conducting layers is provided. A low-conducting layer can be located below the channel and one or more attributes of the low-conducting layer can be configured based on a minimum target operating frequency of the device and a charge-discharge time of a trapped charge targeted for removal by the low-conducting layer or a maximum interfering frequency targeted for suppression using the low-conducting layer. For example, a product of the lateral resistance and a capacitance between the low-conducting layer and the channel can be configured to be larger than an inverse of the minimum target operating frequency and the product can be smaller than at least one of: the charge-discharge time or an inverse of the maximum interfering frequency.

    Abstract translation: 提供了包括一个或多个低导电层的器件。 低导电层可以位于通道下方，并且可以基于器件的最小目标工作频率和针对要被除去的俘获电荷的充电 - 放电时间来配置低导电层的一个或多个属性 低导电层或使用低导电层抑制的最大干扰频率。 例如，横向电阻和低导电层和沟道之间的电容的乘积可以被配置为大于最小目标工作频率的倒数，并且乘积可以小于以下中的至少一个：电荷 - 充电时间或最大干扰频率的倒数。

    Ohmic contact to semiconductor layer
    86.
    发明授权
    Ohmic contact to semiconductor layer 有权
    欧姆接触到半导体层

    公开(公告)号：US08969198B2

    公开(公告)日：2015-03-03

    申请号：US13909621

    申请日：2013-06-04

    Applicant: Sensor Electronic Technology, Inc.

    Inventor： Mikhail Gaevski ,  Grigory Simin ,  Maxim S Shatalov ,  Alexander Dobrinsky ,  Michael Shur ,  Remigijus Gaska

    IPC: H01L21/44 ,  H01L21/768 ,  H01L29/20 ,  H01L29/45

    CPC classification number: H01L21/768 ,  H01L21/28575 ,  H01L21/28587 ,  H01L21/28593 ,  H01L29/2003 ,  H01L29/4175 ,  H01L29/41766 ,  H01L29/452 ,  H01L33/38 ,  H01L2933/0016

    Abstract: A perforating ohmic contact to a semiconductor layer in a semiconductor structure is provided. The perforating ohmic contact can include a set of perforating elements, which can include a set of metal protrusions laterally penetrating the semiconductor layer(s). The perforating elements can be separated from one another by a characteristic length scale selected based on a sheet resistance of the semiconductor layer and a contact resistance per unit length of a metal of the perforating ohmic contact contacting the semiconductor layer. The structure can be annealed using a set of conditions configured to ensure formation of the set of metal protrusions.

    Abstract translation: 提供了与半导体结构中的半导体层的穿孔欧姆接触。 穿孔欧姆接触可以包括一组穿孔元件，其可以包括横向渗透半导体层的一组金属突起。 穿孔元件可以通过基于半导体层的薄层电阻选择的特征长度刻度和接触半导体层的穿孔欧姆接触金属的每单位长度的接触电阻彼此分离。 该结构可以使用一组条件进行退火，所述条件被配置成确保形成该组金属突起。

    Semiconductor device with multiple space-charge control electrodes
    87.
    发明授权
    Semiconductor device with multiple space-charge control electrodes 有权
    具有多个空间充电控制电极的半导体器件

    公开(公告)号：US08878154B2

    公开(公告)日：2014-11-04

    申请号：US13682587

    申请日：2012-11-20

    Applicant: Sensor Electronic Technology, Inc.

    Inventor： Grigory Simin ,  Michael Shur ,  Remigijus Gaska

    IPC: H01L29/02 ,  G05F3/02

    CPC classification number: G05F3/02 ,  H01L29/2003 ,  H01L29/402 ,  H01L29/404 ,  H01L29/42316 ,  H01L29/4232 ,  H01L29/7786 ,  H01L29/872

    Abstract: A circuit including a semiconductor device having a set of space-charge control electrodes is provided. The set of space-charge control electrodes is located between a first terminal, such as a gate or a cathode, and a second terminal, such as a drain or an anode, of the device. The circuit includes a biasing network, which supplies an individual bias voltage to each of the set of space-charge control electrodes. The bias voltage for each space-charge control electrode can be: selected based on the bias voltages of each of the terminals and a location of the space-charge control electrode relative to the terminals and/or configured to deplete a region of the channel under the corresponding space-charge control electrode at an operating voltage applied to the second terminal.

    Abstract translation: 提供了包括具有一组空间电荷控制电极的半导体器件的电路。 该组空间电荷控制电极位于该器件的第一端子（例如栅极或阴极）和第二端子（例如漏极或阳极）之间。 电路包括偏置网络，其向每组空间电荷控制电极中的每一个提供单独的偏置电压。 每个空间电荷控制电极的偏置电压可以是：基于每个端子的偏置电压和空间电荷控制电极相对于端子的位置来选择和/或被配置为消耗通道下方的区域 对应的空间电荷控制电极施加到第二端子的工作电压。

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