公开(公告)号：AU532193B2

公开(公告)日：1983-09-22

申请号：AU5682380

申请日：1980-03-25

Applicant: SONY CORP

Inventor： YAMADA HISAFUMI ,  TOKUHARA MASAHARU ,  KURIKI CHOEI

IPC: H04N5/21 ,  H04N5/52 ,  H04N17/00 ,  H04N5/48

公开(公告)号：CA1130917A

公开(公告)日：1982-08-31

申请号：CA338499

申请日：1979-10-26

Applicant: SONY CORP

Inventor： HONGU MASAYUKI ,  OHMURO SHIGERU ,  TOKUHARA MASAHARU

IPC: H04N5/455 ,  H04N5/62 ,  H04N5/48

Abstract: A television receiver having a video detector synchronously detecting a video intermediate frequency signal by a carrier component which is synchronized with a carrier component of the video intermediate frequency signal, a phase comparator supplied with the video intermediate frequency signal and a signal which is provided by phase-shifting the video intermediate frequency signal by substantially and phase-comparing both or the signals, and a circuit providing a sound intermediate frequency signal from a phase compared output from the phase comparator.

公开(公告)号：DE3012138A1

公开(公告)日：1980-10-09

申请号：DE3012138

申请日：1980-03-28

Applicant: SONY CORP

Inventor： YAMADA HISAFUMI ,  TOKUHARA MASAHARU ,  KURIKI CHOEI

IPC: H04N5/21 ,  H04N5/52 ,  H04N17/00

公开(公告)号：CA1084598A

公开(公告)日：1980-08-26

申请号：CA259325

申请日：1976-08-18

Applicant: SONY CORP

Inventor： HONGU MASAYUKI ,  KAWAKAMI HIROMI ,  TOKUHARA MASAHARU

IPC: H03F3/191 ,  H03D1/22 ,  H03F3/04 ,  H03F3/42 ,  H03F3/45 ,  H04N5/455 ,  H03K5/00 ,  H03K9/06

Abstract: OF TEE DISCLOSURE An amplifier provides a complete video and sound I.F. signal to a synchronous detector switching circuit, and the switching signal to be applied to the switching circuit is obtained from the same amplifier by connecting a grounded base stage, with its emitter impedance, in series with the amplifier load. The grounded base stage has a load tuned to the I.F. carrier frequency and the filtered signal from the grounded base is the signal applied as the switching signal to the synchronous detector switching circuit.

公开(公告)号：DE2944258A1

公开(公告)日：1980-05-08

申请号：DE2944258

申请日：1979-11-02

Applicant: SONY CORP

Inventor： HONGU MASAYUKI ,  OHMURO SHIGERU ,  TOKUHARA MASAHARU

IPC: H03J7/18 ,  H03J7/02 ,  H03J7/08 ,  H04N5/50 ,  H03J3/10

Abstract: An automatic fine tuning (AFT) circuit includes a frequency discriminator for discriminating an intermediate frequency signal, a capacitor supplied with the discriminated intermediate frequency signal to produce an AFT voltage thereacross, a comparator circuit for comparing the AFT voltage with a reference voltage, a first switching transistor controlled by the comparator circuit and which supplies and charges the capacitor with the reference voltage during a channel selection operation when the AFT voltage is less than the reference voltage, a second switching transistor controlled by the comparator circuit and which connects the capacitor to ground to discharge the same during a channel selection operation when the AFT voltage is greater than the reference voltage, and a third switching transistor for rendering the comparator circuit operative during a channel selection operation and inoperative during an AFT operation.

公开(公告)号：DE2920252A1

公开(公告)日：1979-11-22

申请号：DE2920252

申请日：1979-05-18

Applicant: SONY CORP

Inventor： HONGU MASAYUKI ,  TOKUHARA MASAHARU

IPC: H04N5/455 ,  H04N5/50 ,  H04N5/44 ,  H04N9/50

公开(公告)号：DE2811542A1

公开(公告)日：1978-09-21

申请号：DE2811542

申请日：1978-03-16

Applicant: SONY CORP

Inventor： HONGU MASAYUKI ,  KAWAKAMI HIROMI ,  OHMURO SHIGERU ,  TOKUHARA MASAHARU

IPC: H04N5/60 ,  H03G3/34 ,  H04B1/10 ,  H04N5/44 ,  H04N5/455 ,  H03G3/20

Abstract: A muting circuit for a television or AM signal receiver which uses a synchronous detector. The muting circuit includes an input terminal for receiving an amplitude modulated signal, a synchronous detector for detecting such AM signal, a circuit for supplying a reference signal having a predetermined frequency and phase to the synchronous detector, an amplifier, a circuit path for delivering to the amplifier the detected signal produced by the synchronous detector, a level detecting device connected to the output of the synchronous detector for producing an excess signal when the detected signal exceeds a predetermined level, an integrator for producing a muting signal in response to the production over an extended period of time of the excess signal, and a switching device connected to the amplifier for muting the signal produced by the amplifier in response to the production of the muting signal.

公开(公告)号：JP2000004453A

公开(公告)日：2000-01-07

申请号：JP16975898

申请日：1998-06-17

Applicant: SONY CORP

Inventor： KAGITA JUNJI ,  HARADA SHIGERU ,  TOKUHARA MASAHARU

IPC: H04N13/04 ,  H04N5/64

Abstract: PROBLEM TO BE SOLVED: To eliminate a trouble caused by a hard-to-watch image such as a double image in view, displaying a three-dimensional (3D) video when the wearing of spectacles is judged by a communication means and displaying a 2D video when no wearing of spectacles is judged. SOLUTION: The ON/OFF state of a switch 34 attached to spectacles 33 is supplied from the switch 34 to a monitor 31 by a cable 32. Namely, it is supplied from the ON/OFF state of the switch 34 through the cable 32 to the monitor 31 whether a viewer wears the spectacles 33 or not. According to this ON/OFF state of the switch 34, the 2D video/3D video to be displayed on the monitor 31 is switched. Therefore, only when the viewer wears the spectacles 33, the 3D video is displayed on the monitor 31 and when the viewer does not wear the spectacles 33, the 2D video can be displayed so that a hard-to- watch image can be prevented from being displayed on the monitor 31.

公开(公告)号：JPH053789B2

公开(公告)日：1993-01-18

申请号：JP15292383

申请日：1983-08-22

Applicant: SONY CORP

Inventor： TAMURA TAKAHIKO ,  TOKUHARA MASAHARU

IPC: H04N5/59 ,  H04N9/30 ,  H04N9/64

公开(公告)号：JPH04129413A

公开(公告)日：1992-04-30

申请号：JP25155690

申请日：1990-09-20

Applicant: SONY CORP

Inventor： TOKUHARA MASAHARU ,  WATANABE KAZUO ,  TODO HIROBUMI

IPC: H04N19/00 ,  H03H17/00 ,  H03H17/02 ,  H04N11/04 ,  H04N19/42 ,  H04N19/59 ,  H04N19/80 ,  H04N19/85

Abstract: PURPOSE:To realize a sample rate conversion circuit whose circuit scale is reduced by using a multiplier in common for the processing of plural digital data. CONSTITUTION:The circuit is provided with plural 1st latch means 1a latching plural digital data at a 1st sampling clock respectively and plural 2nd latch means 2a latching again each digital data latched by each 1st latch means 1a at a 2nd sampling clock respectively. Then a digital data latched by each of the 2nd latch means 2a is outputted selectively to multipliers M0-Mn at a prescribed order with selection means SW0-SWn and the resulting data is extracted as a time division multiplex data. Since the processing of plural digital data is implemented by the multipliers M0-Mn in common and number of the multipliers M0-Mn with a highest circuit scale is reduced. Thus, the entire circuit is reduced.