公开(公告)号：US20160146933A1

公开(公告)日：2016-05-26

申请号：US14552505

申请日：2014-11-25

Applicant: Texas Instruments Incorporated

Inventor： Sandeep Rao ,  Karthik Subburaj

IPC: G01S13/28 ,  G01S7/02 ,  G01S7/28

CPC classification number: G01S7/023 ,  G01S7/28 ,  G01S7/354 ,  G01S13/34 ,  G01S13/343 ,  G01S13/38 ,  G01S13/583 ,  G01S13/931

Abstract: Radar detection of an object is achieved by identifying a first range associated with a possible object based on a first return from a first radar transmission having a first chirp rate, and identifying a second range associated with the possible object based on a second return from a second radar transmission having a second chirp rate that differs from the first chirp rate. The first and second ranges are evaluated together to determine whether the possible object is a true object.

Abstract translation: 通过基于来自具有第一啁啾率的第一雷达传输的第一返回来识别与可能对象相关联的第一范围，并且基于来自第一啁啾率的第二返回来识别与可能对象相关联的第二范围来实现对象的雷达检测 第二雷达传输具有与第一啁啾率不同的第二啁啾率。 一起评估第一和第二范围以确定可能的对象是否是真实对象。

公开(公告)号：US20250138148A1

公开(公告)日：2025-05-01

申请号：US18499181

申请日：2023-10-31

Applicant: Texas Instruments Incorporated

Inventor： Karthik Subburaj ,  Piyush Soni ,  Vashishth Dudhia ,  Ryan Smith ,  Kavithaa Rajagopalan ,  Karthik Ramasubramanian ,  Shankar Ram Narayana Moorthy ,  Indu Prathapan ,  Samala Sreekiran

IPC: G01S7/40 ,  G01S13/32

Abstract: In described examples, a frequency modulated continuous wave (FMCW) radar includes a reference clock, a phase locked loop (PLL), a pulse generator, a counter, a chirp ramp control circuit, and a synchronization state machine. The reference clock generates a reference clock signal. The PLL generates a feedback clock signal in response to the reference clock signal, and an output signal in response to the feedback clock signal. The pulse generator outputs a chirp start pulse in response to the reference clock signal. The counter increments a count in response to the feedback clock signal. The synchronization state machine provides a chirp ramp signal to a chirp ramp control circuit in response to the reference clock signal, the feedback clock signal, the chirp start pulse, and the count. The chirp ramp control circuit causes the PLL to ramp a frequency of the output signal in response to the chirp ramp signal.

公开(公告)号：US12248091B2

公开(公告)日：2025-03-11

申请号：US17486435

申请日：2021-09-27

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Karthik Subburaj ,  Sandeep Rao

IPC: G01S7/35 ,  G01S13/58 ,  G01S13/931

Abstract: An apparatus comprises processor cores and computer-readable mediums storing machine instructions for the processor cores. When executing the machine instructions, the processor cores obtain received signals for transmitted chirps from a radar sensor circuit. Each transmitted chirp comprises an A chirp segment, a time gap, and a B chirp segment, respectively. The processor cores sample the received signals to obtain sampled data matrices M1(A) for the A chirp segments and M1(B) for the B chirp segments. The processor cores perform a first Fourier transform (FT) on each column of M1(A) and M1(B) to obtain velocity matrices M2(A) and M2(B), respectively. The processor cores apply a phase compensation factor to M2(B) to obtain a phase corrected velocity matrix M2(B′), and concatenate M2(A) and M2(B′) to obtain an aggregate velocity matrix M2(A&B′). The processor cores perform a second FT on each row of M2(A&B′) to obtain a range and velocity matrix M3(A&B′).

公开(公告)号：US20240353528A1

公开(公告)日：2024-10-24

申请号：US18341296

申请日：2023-06-26

Applicant: Texas Instruments Incorporated

Inventor： Karthik Subburaj ,  Anil Mani

IPC: G01S7/35 ,  G01S7/288 ,  G01S7/40

CPC classification number: G01S7/356 ,  G01S7/2883 ,  G01S7/4056

Abstract: Signal processing comprising, first, determining a plurality of fast Fourier transform (FFT) values corresponding to each sample in a plurality of signal samples, second, variably compressing ones of the FFT values at different non-zero levels of compression, and third, storing the variably compressed ones of the FFT values.

公开(公告)号：US12007462B2

公开(公告)日：2024-06-11

申请号：US17351654

申请日：2021-06-18

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Karthik Subburaj ,  Karthik Ramasubramanian ,  Shailesh Joshi ,  Kameswaran Vengattaramane ,  Indu Prathapan

IPC: G01S13/04 ,  G01S7/35 ,  G06F16/22 ,  G06F16/901 ,  G06F17/14

CPC classification number: G01S13/04 ,  G01S7/35 ,  G06F16/2264 ,  G06F16/9017 ,  G06F17/142

Abstract: A system includes a memory configured to store a two-dimensional data structure that includes radar data arranged such that radar data of a first transmitter is separated from radar data of a second transmitter by a Doppler offset in the two-dimensional data structure. The system also includes a data fetch mechanism that includes a lookup table (LUT) applied on either of two dimensions. The lookup table is configured to store a data fetch location in the two-dimensional data structure, where the data fetch location indicates a location from which to fetch a subset of the radar data from the two-dimensional data structure and the data fetch mechanism is configured to fetch the subset of the radar data from the two-dimensional data structure based on the LUT. The system includes a processor configured to perform a fast Fourier transform (FFT) on the fetched subset of the radar data.

公开(公告)号：US20240183939A1

公开(公告)日：2024-06-06

申请号：US18420133

申请日：2024-01-23

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Sujaata Ramalingam ,  Karthik Subburaj ,  Pankaj Gupta ,  Anil Varghese Mani ,  Karthik Ramasubramanian ,  Indu Prathapan

IPC: G01S7/292 ,  G01S7/40 ,  G01S13/524

CPC classification number: G01S7/2922 ,  G01S7/4004 ,  G01S13/5246

Abstract: In a system a register stores data samples and includes a cell under test (CUT) in which a test data sample is stored, a first window of multiple cells on one side of the CUT, and a second window of multiple cells on the other side of the CUT. A rank determining circuit receives an incoming data sample entering the register and data sample(s) currently in cell(s) in the first window of multiple cells. A sorted index array stores ranks of data samples that are stored in the register. Comparing and selection circuitry selects a Kth smallest index from the sorted index array and a corresponding data sample from the register. A target comparator receives the test data sample and the data sample corresponding to the Kth smallest index of the sorted index array, and outputs a target detection signal.

公开(公告)号：US11988769B2

公开(公告)日：2024-05-21

申请号：US17856109

申请日：2022-07-01

Applicant: Texas Instruments Incorporated

Inventor： Sandeep Rao ,  Karthik Subburaj ,  Dan Wang ,  Adeel Ahmad

IPC: G01S13/34 ,  G01S7/35 ,  G01S13/42 ,  G01S13/92

CPC classification number: G01S7/354 ,  G01S13/343 ,  G01S13/42 ,  G01S13/92 ,  G01S7/356

Abstract: In accordance with described examples, a method determines if a velocity of an object detected by a radar is greater than a maximum velocity by receiving on a plurality of receivers at least one frame of chirps transmitted by at least two transmitters and reflected off of the object. A velocity induced phase shift (φd) in a virtual array vector S of signals received by each receiver corresponding to a sequence of chirps (frame) transmitted by each transmitter is estimated. Phases of each element of virtual array vector S are corrected using φd to generate a corrected virtual array vector Sc. A first Fourier transform is performed on the corrected virtual array vector Sc to generate a corrected virtual array spectrum to detect a signature that indicates that the object has an absolute velocity greater than a maximum velocity.

公开(公告)号：US11815621B2

公开(公告)日：2023-11-14

申请号：US17368319

申请日：2021-07-06

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Sriram Murali ,  Karthik Subburaj ,  Karthik Ramasubramanian

IPC: G01S7/35 ,  G01S7/40 ,  G01S13/931

CPC classification number: G01S7/352 ,  G01S7/4021 ,  G01S13/931 ,  G01S7/358 ,  G01S7/406

Abstract: A radar system is provided that includes a receive channel configured to receive a reflected signal and to generate a first digital intermediate frequency (IF) signal based on the reflected signal, a reference receive channel configured to receive a reflected signal and to generate a second digital IF signal based on the reflected signal, and digital mismatch compensation circuitry coupled to receive the first digital IF signal and the second digital IF signal, the digital mismatch compensation circuitry configured to process the first digital IF signal and the second digital IF signal to compensate for mismatches between the receive channel and the reference receive channel.

公开(公告)号：US11650285B2

公开(公告)日：2023-05-16

申请号：US16036011

申请日：2018-07-16

Applicant: Texas Instruments Incorporated

Inventor： Sachin Bharadwaj ,  Karthik Subburaj

IPC: G01S13/34 ,  G01S7/35 ,  G01S13/58 ,  G01S7/40 ,  H03L7/06 ,  H03L7/08 ,  H03L7/12

CPC classification number: G01S7/35 ,  G01S7/4008 ,  G01S13/343 ,  G01S13/583 ,  H03L7/06 ,  H03L7/0805 ,  H03L7/12 ,  G01S13/584

Abstract: The disclosure provides a radar apparatus. The radar apparatus includes a transmit unit that generates a first signal in response to a reference clock and a feedback clock. The first signal is scattered by one or more obstacles to generate a second signal. A receive unit receives the second signal and generates N samples corresponding to the second signal. N is an integer. A conditioning circuit is coupled to the transmit unit and the receive unit. The conditioning circuit receives the N samples corresponding to the second signal, and generates N new samples using an error between the feedback clock and the reference clock.

公开(公告)号：US20230094118A1

公开(公告)日：2023-03-30

申请号：US17486435

申请日：2021-09-27

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Karthik Subburaj ,  Sandeep Rao

IPC: G01S7/35 ,  G01S13/931 ,  G01S13/58

Abstract: An apparatus comprises processor cores and computer-readable mediums storing machine instructions for the processor cores. When executing the machine instructions, the processor cores obtain received signals for transmitted chirps from a radar sensor circuit. Each transmitted chirp comprises an A chirp segment, a time gap, and a B chirp segment, respectively. The processor cores sample the received signals to obtain sampled data matrices M1(A) for the A chirp segments and M1(B) for the B chirp segments. The processor cores perform a first Fourier transform (FT) on each column of M1(A) and M1(B) to obtain velocity matrices M2(A) and M2(B), respectively. The processor cores apply a phase compensation factor to M2(B) to obtain a phase corrected velocity matrix M2(B′), and concatenate M2(A) and M2(B′) to obtain an aggregate velocity matrix M2(A&B′). The processor cores perform a second FT on each row of M2(A&B′) to obtain a range and velocity matrix M3(A&B′).