公开(公告)号：US20170200721A1

公开(公告)日：2017-07-13

申请号：US15045258

申请日：2016-02-17

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chien-Hung Chen ,  Shih-Hsien Huang ,  Yu-Ru Yang ,  Chia-Hsun Tseng ,  Cheng-Tzung Tsai ,  Chun-Yuan Wu

IPC: H01L27/092 ,  H01L21/02 ,  H01L21/306 ,  H01L29/165 ,  H01L21/8238

Abstract: A semiconductor device includes a substrate, a first well formed in the substrate, a second well formed in the substrate, a first fin formed on the first well, and a second fin formed on the second well. The first well includes a first conductivity type, the second well includes a second conductivity type, and the first conductivity type and the second conductivity type are complementary to each other. The substrate includes a first semiconductor material. The first fin and the second fin include the first semiconductor material and a second semiconductor material. A lattice constant of the second semiconductor material is larger than a lattice constant of the first semiconductor material. The first semiconductor material in the first fin includes a first concentration, the first semiconductor material in the second fin includes a second concentration, and the second concentration is larger than the first concentration.

公开(公告)号：US20170098692A1

公开(公告)日：2017-04-06

申请号：US14936370

申请日：2015-11-09

Applicant: United Microelectronics Corp.

Inventor： Huai-Tzu Chiang ,  Sheng-Hao Lin ,  Hao-Ming Lee ,  Yu-Ru Yang ,  Shih-Hsien Huang ,  Chien-Hung Chen ,  Chun-Yuan Wu ,  Cheng-Tzung Tsai

IPC: H01L29/06 ,  H01L21/768 ,  H01L29/66 ,  H01L21/225 ,  H01L29/78 ,  H01L29/10

CPC classification number: H01L29/0615 ,  H01L21/2253 ,  H01L21/76802 ,  H01L21/76871 ,  H01L29/1033 ,  H01L29/1054 ,  H01L29/66795 ,  H01L29/785

Abstract: Provided is a FinFET including a substrate, at least one fin and at least one gate. A portion of the at least one fin is embedded in the substrate. The at least one fin includes, from bottom to top, a seed layer, a stress relaxation layer and a channel layer. The at least one gate is across the at least one fin. A method of forming a FinFET is further provided.

公开(公告)号：US09461150B2

公开(公告)日：2016-10-04

申请号：US14979594

申请日：2015-12-28

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chin-Cheng Chien ,  Hsin-Kuo Hsu ,  Chih-Chien Liu ,  Chin-Fu Lin ,  Chun-Yuan Wu

IPC: H01L29/66 ,  H01L21/02 ,  H01L29/10 ,  H01L29/78 ,  H01L29/06 ,  H01L21/311 ,  H01L29/36

CPC classification number: H01L29/66795 ,  H01L21/0228 ,  H01L21/02532 ,  H01L21/30604 ,  H01L21/31111 ,  H01L29/06 ,  H01L29/0657 ,  H01L29/1054 ,  H01L29/36 ,  H01L29/7848 ,  H01L29/785 ,  H01L29/7853

Abstract: A method for fabricating semiconductor device with fin-shaped structure is disclosed. The method includes the steps of: forming a fin-shaped structure on a substrate; forming a first dielectric layer on the substrate and the fin-shaped structure; depositing a second dielectric layer on the first dielectric layer; etching back a portion of the second dielectric layer; removing part of the first dielectric layer to expose a top surface and part of the sidewall of the fin-shaped structure; forming an epitaxial layer to cover the exposed top surface and part of the sidewall of the fin-shaped structure; and removing a portion of the second dielectric layer.

Abstract translation: 公开了一种制造具有鳍状结构的半导体器件的方法。 该方法包括以下步骤：在衬底上形成鳍状结构; 在所述基板上形成第一电介质层和所述鳍状结构; 在所述第一电介质层上沉积第二电介质层; 蚀刻第二介电层的一部分; 去除所述第一电介质层的一部分以暴露所述鳍状结构的顶表面和所述侧壁的一部分; 形成外延层以覆盖所述鳍状结构的暴露的顶表面和所述侧壁的一部分; 以及去除所述第二电介质层的一部分。

公开(公告)号：US20150206803A1

公开(公告)日：2015-07-23

申请号：US14158857

申请日：2014-01-19

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Wei-Hsin Liu ,  Tzu-Chin Wu ,  Jei-Ming Chen ,  Yu-Ren Wang ,  Chun-Yuan Wu ,  Chin-Fu Lin

IPC: H01L21/8234 ,  H01L21/311 ,  H01L21/02 ,  H01L21/3105

CPC classification number: H01L21/823462 ,  H01L21/31116 ,  H01L21/76837 ,  H01L21/823475

Abstract: A method of forming an inter-level dielectric layer including the following step is provided. Two gate structures are formed on a substrate. A first oxide layer is formed to conformally cover the two gate structures and the substrate. The first oxide layer is etched ex-situ by a high density plasma (HDP) etching process. A second oxide layer is formed in-situ on the first oxide layer and fills a gap between the two gate structures by a high density plasma (HDP) depositing process.

Abstract translation: 提供一种形成包括以下步骤的层间电介质层的方法。 在基板上形成两个栅极结构。 形成第一氧化物层以保形地覆盖两个栅极结构和衬底。 通过高密度等离子体（HDP）蚀刻工艺非原位蚀刻第一氧化物层。 在第一氧化物层上原地形成第二氧化物层，并通过高密度等离子体（HDP）沉积工艺填充两个栅极结构之间的间隙。

公开(公告)号：US09076652B2

公开(公告)日：2015-07-07

申请号：US13902870

申请日：2013-05-27

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ming-Hua Chang ,  Chun-Yuan Wu ,  Chin-Cheng Chien ,  Tien-Wei Yu ,  Yu-Shu Lin ,  Szu-Hao Lai

IPC: H01L21/20 ,  H01L21/02

CPC classification number: H01L29/7848 ,  H01L21/0245 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02639 ,  H01L21/3003 ,  H01L21/30604 ,  H01L21/324 ,  H01L29/0847 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66636

Abstract: A semiconductor process includes the following steps. Two gates are formed on a substrate. A recess is formed in the substrate beside the gates. A surface modification process is performed on a surface of the recess to modify the shape of the recess and change the contents of the surface.

Abstract translation: 半导体工艺包括以下步骤。 在基板上形成两个栅极。 在栅极旁边的基板中形成凹部。 在凹部的表面上进行表面改性处理，以改变凹部的形状并改变表面的内容物。

公开(公告)号：US20140349467A1

公开(公告)日：2014-11-27

申请号：US13902870

申请日：2013-05-27

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ming-Hua Chang ,  Chun-Yuan Wu ,  Chin-Cheng Chien ,  Tien-Wei Yu ,  Yu-Shu Lin ,  Szu-Hao Lai

IPC: H01L21/02

CPC classification number: H01L29/7848 ,  H01L21/0245 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02639 ,  H01L21/3003 ,  H01L21/30604 ,  H01L21/324 ,  H01L29/0847 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66636

Abstract: A semiconductor process includes the following steps. Two gates are formed on a substrate. A recess is formed in the substrate beside the gates. A surface modification process is performed on a surface of the recess to modify the shape of the recess and change the contents of the surface.

Abstract translation: 半导体工艺包括以下步骤。 在基板上形成两个栅极。 在栅极旁边的基板中形成凹部。 在凹部的表面上进行表面改性处理，以改变凹部的形状并改变表面的内容物。

公开(公告)号：US08853060B1

公开(公告)日：2014-10-07

申请号：US13902862

申请日：2013-05-27

Applicant: United Microelectronics Corp.

Inventor： Szu-Hao Lai ,  Chun-Yuan Wu ,  Chin-Cheng Chien ,  Tien-Wei Yu ,  Ming-Hua Chang ,  Yu-Shu Lin ,  Tsai-Yu Wen ,  Hsin-Kuo Hsu

IPC: H01L21/20 ,  H01L21/02

CPC classification number: H01L21/02532 ,  H01L21/0237 ,  H01L21/0245 ,  H01L21/02579 ,  H01L21/0262 ,  H01L21/02639 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/66636 ,  H01L29/7848

Abstract: An epitaxial process includes the following step. A recess is formed in a substrate. A seeding layer is formed to cover a surface of the recess. A buffer layer is formed on the seeding layer. An etching process is performed on the buffer layer to homogenize and shape the buffer layer. An epitaxial layer is formed on the homogenized flat bottom shape buffer layer.

Abstract translation: 外延工艺包括以下步骤。 在基板上形成凹部。 形成接合层以覆盖凹部的表面。 在接种层上形成缓冲层。 对缓冲层进行蚀刻处理，使缓冲层均匀化并形成。 在均质化的平底形状缓冲层上形成外延层。

公开(公告)号：US20140117455A1

公开(公告)日：2014-05-01

申请号：US13662561

申请日：2012-10-29

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chih-Chien Liu ,  Chun-Yuan Wu ,  Chin-Fu Lin ,  Chin-Cheng Chien ,  Chia-Lin Hsu

IPC: H01L21/336 ,  H01L29/78

CPC classification number: H01L29/785 ,  H01L21/02225 ,  H01L21/764 ,  H01L27/11 ,  H01L29/66484 ,  H01L29/66795

Abstract: A multigate field effect transistor includes two fin-shaped structures and a dielectric layer. The fin-shaped structures are located on a substrate. The dielectric layer covers the substrate and the fin-shaped structures. At least two voids are located in the dielectric layer between the two fin-shaped structures. Moreover, the present invention also provides a multigate field effect transistor process for forming said multigate field effect transistor including the following steps. Two fin-shaped structures are formed on a substrate. A dielectric layer covers the substrate and the two fin-shaped structures, wherein at least two voids are formed in the dielectric layer between the two fin-shaped structures.

Abstract translation: 多栅场效应晶体管包括两个鳍状结构和介电层。 鳍状结构位于基底上。 电介质层覆盖基板和鳍状结构。 在两个鳍状结构之间的电介质层中至少有两个空隙。 此外，本发明还提供了一种用于形成所述多栅极场效应晶体管的多栅场效应晶体管工艺，包括以下步骤。 在基板上形成两个鳍状结构。 介电层覆盖基板和两个鳍状结构，其中在两个鳍状结构之间的电介质层中形成至少两个空隙。

公开(公告)号：US20140106568A1

公开(公告)日：2014-04-17

申请号：US14142940

申请日：2013-12-30

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chun-Yuan Wu ,  Chih-Chien Liu ,  Chin-Fu Lin ,  Po-Chun Chen

IPC: H01L21/311

CPC classification number: H01L21/31144 ,  H01L21/76802

Abstract: The present invention provides a method of forming an opening on a semiconductor substrate. First, a substrate is provided. Then a dielectric layer and a cap layer are formed on the substrate. A ratio of a thickness of the dielectric layer and a thickness of the cap layer is substantially between 15 and 1.5. Next, a patterned boron nitride layer is formed on the cap layer. Lastly, an etching process is performed by using the patterned hard mask as a mask to etch the cap layer and the dielectric layer so as to form an opening in the cap layer and the dielectric layer.

Abstract translation: 本发明提供一种在半导体衬底上形成开口的方法。 首先，提供基板。 然后在基板上形成介电层和盖层。 电介质层的厚度和盖层的厚度之比基本上在15和1.5之间。 接下来，在盖层上形成图案化的氮化硼层。 最后，通过使用图案化的硬掩模作为掩模来执行蚀刻工艺，以蚀刻覆盖层和电介质层，以在盖层和电介质层中形成开口。

公开(公告)号：US20130288446A1

公开(公告)日：2013-10-31

申请号：US13928366

申请日：2013-06-26

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ted Ming-Lang Guo ,  Chin-Cheng Chien ,  Shu-Yen Chan ,  Ling-Chun Chou ,  Tsung-Hung Chang ,  Chun-Yuan Wu

IPC: H01L29/66

CPC classification number: H01L29/66477 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/7843 ,  H01L29/7847

Abstract: A semiconductor structure including a substrate and a gate structure disposed on the substrate is disclosed. The gate structure includes a gate dielectric layer disposed on the substrate, a gate material layer disposed on the gate dielectric layer and an outer spacer with a rectangular cross section. The top surface of the outer spacer is lower than the top surface of the gate material layer.

Abstract translation: 公开了一种包括衬底和设置在衬底上的栅极结构的半导体结构。 栅极结构包括设置在基板上的栅极介质层，设置在栅极介电层上的栅极材料层和具有矩形横截面的外部间隔物。 外隔离物的顶表面比栅极材料层的顶表面低。