公开(公告)号：US10290638B1

公开(公告)日：2019-05-14

申请号：US15964089

申请日：2018-04-27

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Yi-Wei Chen ,  Tsun-Min Cheng ,  Shih-Fang Tzou ,  Chih-Chieh Tsai ,  Kai-Jiun Chang

IPC: H01L27/108 ,  H01L23/532 ,  H01L21/285 ,  H01L21/768 ,  H01L23/528 ,  H01L21/02 ,  H01L21/3105 ,  H01L21/265 ,  H01L29/10 ,  H01L21/306

Abstract: A method of forming dynamic random access memory (DRAM) device, comprises the following steps. First of all, a plurality of active areas is formed in a substrate along a first direction. Next, a plurality of buried gates disposed in the substrate is formed along a second trench extending along a second direction across the first direction. Then, a plurality of bit lines is formed over the buried gates and extended along a third direction across the first direction and the second direction, wherein each of the bit lines comprises a polysilicon layer, a barrier layer and a metal layer and the barrier layer is formed through a radio frequency physical vapor deposition (RF-PVD) process.

公开(公告)号：US10276650B2

公开(公告)日：2019-04-30

申请号：US15927103

申请日：2018-03-21

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Tzu-Chin Wu ,  Wei-Hsin Liu ,  Yi-Wei Chen ,  Chia-Lung Chang ,  Jui-Min Lee ,  Po-Chun Chen ,  Li-Wei Feng ,  Ying-Chiao Wang ,  Wen-Chieh Lu ,  Chien-Ting Ho ,  Tsung-Ying Tsai ,  Kai-Ping Chen

IPC: H01L27/108 ,  H01L49/02 ,  H01L29/94

Abstract: A semiconductor memory device includes a semiconductor substrate, a first support layer, a first electrode, a capacitor dielectric layer, and a second electrode. The first support layer is disposed on the semiconductor substrate. The first electrode is disposed on the semiconductor substrate and penetrates the first support layer. The capacitor dielectric layer is disposed on the first electrode. The second electrode is disposed on the semiconductor substrate, and at least a part of the capacitor dielectric layer is disposed between the first electrode and the second electrode. The first support layer includes a carbon doped nitride layer, and a carbon concentration of a bottom portion of the first support layer is higher than a carbon concentration of a top portion of the first support layer.

公开(公告)号：US20190109139A1

公开(公告)日：2019-04-11

申请号：US16053748

申请日：2018-08-02

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Tzu-Chin Wu ,  Chao-An Liu ,  Ching-Hsiang Chang ,  Yi-Wei Chen

IPC: H01L27/108 ,  H01L21/308 ,  H01L21/02 ,  H01L21/306

CPC classification number: H01L27/10891 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02211 ,  H01L21/02271 ,  H01L21/0273 ,  H01L21/0332 ,  H01L21/30604 ,  H01L21/3081 ,  H01L21/3086 ,  H01L27/10823 ,  H01L27/10855 ,  H01L27/10876

Abstract: A method of fabricating a DRAM includes providing a substrate. Later, a first mask layer is formed to cover the substrate. The first mask layer includes a hydrogen-containing silicon nitride layer and a silicon oxide layer. The hydrogen-containing silicon nitride layer has the chemical formula: SixNyHz, wherein x is between 4 and 8, y is between 3.5 and 9.5, and z equals 1. After that, the first mask layer is patterned to form a first patterned mask layer. Next, the substrate is etched by taking the first patterned mask layer as a mask to form a word line trench. Subsequently, the first patterned mask layer is removed entirely. Finally, a word line is formed in the word line trench.

公开(公告)号：US20190013320A1

公开(公告)日：2019-01-10

申请号：US15986780

申请日：2018-05-22

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Tzu-Chieh Chen ,  Pin-Hong Chen ,  Chih-Chieh Tsai ,  Chia-Chen Wu ,  Yi-An Huang ,  Kai-Jiun Chang ,  Tsun-Min Cheng ,  Yi-Wei Chen

IPC: H01L27/108 ,  H01L23/31

Abstract: A semiconductor memory device is provided, and which includes a substrate, plural gates, plural plugs, a capacitor structure and a conducting cap layer. The gates are disposed within the substrate, and the plugs are disposed on the substrate, with each plug electrically connected to two sides of each gate on the substrate. The capacitor structure is disposed on the substrate, and the capacitor structure includes plural capacitors, with each capacitor electrically connected to the plugs respectively. The conducting cap layer covers the top surface and sidewalls of the capacitor structure. Also, the semiconductor memory device further includes an adhesion layer and an insulating layer. The adhesion layer covers the conducting cap layer and the capacitor structure, and the insulating layer covers the adhesion layer.

公开(公告)号：US20180190662A1

公开(公告)日：2018-07-05

申请号：US15854825

申请日：2017-12-27

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Tzu-Chin Wu ,  Wei-Hsin Liu ,  Yi-Wei Chen ,  Mei-Ling Chen ,  Chia-Lung Chang ,  Ching-Hsiang Chang ,  Jui-Min Lee ,  Tsun-Min Cheng ,  Lin-Chen Lu ,  Shih-Fang Tzou ,  Kai-Jiun Chang ,  Chih-Chieh Tsai ,  Tzu-Chieh Chen ,  Chia-Chen Wu

IPC: H01L27/108 ,  H01L21/033 ,  H01L23/532 ,  H01L23/528 ,  H01L21/768 ,  H01L21/285

CPC classification number: H01L27/10885 ,  H01L21/0332 ,  H01L21/0337 ,  H01L21/28568 ,  H01L21/32139 ,  H01L21/76846 ,  H01L21/76877 ,  H01L23/528 ,  H01L23/53266 ,  H01L23/53271 ,  H01L27/10823 ,  H01L27/10876

Abstract: A method of forming a bit line gate structure of a dynamic random access memory (DRAM) includes the following. A hard mask layer is formed on a metal stack by a chemical vapor deposition process importing nitrogen (N2) gases and then importing amonia (NH3) gases. The present invention also provides a bit line gate structure of a dynamic random access memory (DRAM) including a metal stack and a hard mask. The metal stack includes a polysilicon layer, a titanium layer, a titanium nitride layer, a first tungsten nitride layer, a tungsten layer and a second tungsten nitride layer stacked from bottom to top. The hard mask is disposed on the metal stack.

公开(公告)号：US09966434B2

公开(公告)日：2018-05-08

申请号：US15632399

申请日：2017-06-26

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ming-Shiou Hsieh ,  Chun-Yao Yang ,  Shi-You Liu ,  Rong-Sin Lin ,  Han-Ting Yen ,  Yi-Wei Chen ,  I-Cheng Hu ,  Yu-Shu Lin ,  Neng-Hui Yang

IPC: H01L29/08 ,  H01L21/02 ,  H01L29/165 ,  H01L29/36 ,  H01L21/265 ,  H01L21/324 ,  H01L29/167 ,  H01L21/283 ,  H01L21/768 ,  H01L21/8234 ,  H01L29/417 ,  H01L29/78 ,  H01L29/06 ,  H01L27/088

CPC classification number: H01L29/0847 ,  H01L21/02532 ,  H01L21/02639 ,  H01L21/2257 ,  H01L21/265 ,  H01L21/26513 ,  H01L21/283 ,  H01L21/324 ,  H01L21/76877 ,  H01L21/76897 ,  H01L21/823425 ,  H01L21/823475 ,  H01L23/485 ,  H01L23/528 ,  H01L23/53252 ,  H01L27/088 ,  H01L27/0886 ,  H01L29/0649 ,  H01L29/161 ,  H01L29/165 ,  H01L29/167 ,  H01L29/36 ,  H01L29/41783 ,  H01L29/665 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7834 ,  H01L29/7848

Abstract: A semiconductor device includes a substrate including a plurality of transistor devices formed thereon, at least an epitaxial structure formed in between the transistor devices, and a tri-layered structure formed on the epitaxial structure. The epitaxial structure includes a first semiconductor material and a second semiconductor material, and a lattice constant of the second semiconductor material is larger than a lattice constant of the first semiconductor material. The tri-layered structure includes an undoped epitaxial layer, a metal-semiconductor compound layer, and a doped epitaxial layer sandwiched in between the undoped epitaxial layer and the metal-semiconductor compound layer. The undoped epitaxial layer and the doped epitaxial layer include at least the second semiconductor material.

公开(公告)号：US09859123B1

公开(公告)日：2018-01-02

申请号：US15472308

申请日：2017-03-29

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Chia-Chen Wu ,  Pin-Hong Chen ,  Kai-Jiun Chang ,  Yi-An Huang ,  Chih-Chieh Tsai ,  Tzu-Chieh Chen ,  Tsun-Min Cheng ,  Yi-Wei Chen

IPC: H01L21/28 ,  H01L21/285 ,  H01L21/768 ,  H01L21/321 ,  H01L29/66

CPC classification number: H01L21/28518 ,  H01L21/321 ,  H01L21/76889 ,  H01L29/665

Abstract: A method for fabricating a semiconductor device is disclosed. A substrate having a conductive region is provided. A metal layer is deposited on the conductive region. The metal layer reacts with the conductive region to form a first metal silicide layer. A TiN layer is deposited on the metal layer. A SiN layer is deposited on the TiN layer. An annealing process is performed to convert the first metal silicide layer into a second metal silicide layer.

公开(公告)号：US20170345938A1

公开(公告)日：2017-11-30

申请号：US15681417

申请日：2017-08-20

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Sheng-Hsu Liu ,  Jhen-cyuan Li ,  Chih-Chung Chen ,  Man-Ling Lu ,  Chung-Min Tsai ,  Yi-Wei Chen

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/165

CPC classification number: H01L29/7851 ,  H01L21/764 ,  H01L29/0649 ,  H01L29/0692 ,  H01L29/165 ,  H01L29/66795 ,  H01L29/7848 ,  Y02E10/50

Abstract: A fin structure for a semiconductor device, such as a FinFET structure, has first and second semiconductor layers and an air gap between the layers. The second semiconductor layer includes a recessed portion, the air gap is located in the recessed portion, and the recessed portion has an upwardly-opening acute angle in the range from about 10° to about 55°. The air gap may prevent current leakage. A FinFET device may be manufactured by first recessing and then epitaxially re-growing a source/drain fin, with the regrowth starting over a tubular air gap.

公开(公告)号：US09786510B2

公开(公告)日：2017-10-10

申请号：US14512475

申请日：2014-10-13

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Wen-Jiun Shen ,  Ssu-I Fu ,  Yen-Liang Wu ,  Chia-Jong Liu ,  Yu-Hsiang Hung ,  Chung-Fu Chang ,  Man-Ling Lu ,  Yi-Wei Chen

IPC: H01L21/308 ,  H01L27/088 ,  H01L21/8234 ,  H01L21/306 ,  H01L21/02

CPC classification number: H01L21/308 ,  H01L21/02238 ,  H01L21/30604 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/66818

Abstract: A fin-shaped structure includes a substrate having a first fin-shaped structure located in a first area and a second fin-shaped structure located in a second area, wherein the second fin-shaped structure includes a ladder-shaped cross-sectional profile part. The present invention also provides two methods of forming this fin-shaped structure. In one case, a substrate having a first fin-shaped structure and a second fin-shaped structure is provided. A treatment process is performed to modify an external surface of the top of the second fin-shaped structure, thereby forming a modified part. A removing process is performed to remove the modified part through a high removing selectivity to the first fin-shaped structure and the second fin-shaped structure, and the modified part, thereby the second fin-shaped structure having a ladder-shaped cross-sectional profile part is formed.

公开(公告)号：US09780199B2

公开(公告)日：2017-10-03

申请号：US14862165

申请日：2015-09-23

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ching-Wen Hung ,  Chih-Sen Huang ,  Yi-Wei Chen ,  Shih-Fang Tzou

IPC: H01L21/768 ,  H01L29/66

CPC classification number: H01L29/66795 ,  H01L21/76897 ,  H01L29/41791 ,  H01L29/66545

Abstract: A method of forming a semiconductor device includes following steps. Firstly, a gate structure is formed on a substrate, and two source/drain regions are formed. Then, a contact etching stop layer (CESL) is formed to cover the source/drain regions, and a first interlayer dielectric (ILD) layer is formed on the CESL. Next, a replace metal gate process is performed to form a metal gate and a capping layer on the metal gate, and a second ILD layer is formed on the first ILD layer. Following these, a first opening is formed in the second and first ILD layers to partially expose the CESL, and a second opening is formed in the second ILD to expose the capping layer. Finally, the CESL and the capping layer are simultaneously removed.