公开(公告)号：US07386706B2

公开(公告)日：2008-06-10

申请号：US10716568

申请日：2003-11-20

Applicant: Craig Hansen ,  John Moussouris

Inventor： Craig Hansen ,  John Moussouris

IPC: G06F9/34

CPC classification number: G06F9/30014 ,  G06F9/30018 ,  G06F9/30025 ,  G06F9/30029 ,  G06F9/30032 ,  G06F9/30036 ,  G06F9/3004 ,  G06F9/30043 ,  G06F9/30054 ,  G06F9/30087 ,  G06F9/30101 ,  G06F9/30109 ,  G06F9/30112 ,  G06F9/3012 ,  G06F9/30123 ,  G06F9/30145 ,  G06F9/3016 ,  G06F9/30167 ,  G06F9/3816 ,  G06F9/3824 ,  G06F9/383 ,  G06F9/3851 ,  G06F9/3861 ,  G06F9/3873 ,  G06F9/3885 ,  G06F15/7832

Abstract: A system and software for improving the performance of processors by incorporating an execution unit operable to decode and execute single instructions in an instruction set comprising (a) group instructions that operate on a plurality of data elements in partitioned fields of a register to produce a catenated result, (b) aligned memory operations that move data between memory and register where the memory operand is aligned, and (c) unaligned memory operations where the memory operand is unaligned.

Abstract translation: 一种用于通过并入执行单元的系统和软件，所述执行单元可操作以对指令集中的单个指令进行解码和执行，所述指令集包括：（a）在寄存器的分割字段中对多个数据元素进行操作的组指令， 结果，（b）对齐的存储器操作，在存储器和寄存器之间移动数据，存储器操作数对齐，以及（c）存储器操作数未对齐的未对齐的存储器操作。

公开(公告)号：US20080104376A1

公开(公告)日：2008-05-01

申请号：US11842025

申请日：2007-10-29

Applicant: Craig Hansen ,  John Moussouris

Inventor： Craig Hansen ,  John Moussouris

IPC: G06F9/302

CPC classification number: G06F9/30014 ,  G06F9/30018 ,  G06F9/30025 ,  G06F9/30029 ,  G06F9/30032 ,  G06F9/30036 ,  G06F9/3004 ,  G06F9/30043 ,  G06F9/30054 ,  G06F9/30087 ,  G06F9/30101 ,  G06F9/30109 ,  G06F9/30112 ,  G06F9/3012 ,  G06F9/30123 ,  G06F9/30145 ,  G06F9/3016 ,  G06F9/30167 ,  G06F9/3816 ,  G06F9/3824 ,  G06F9/383 ,  G06F9/3851 ,  G06F9/3861 ,  G06F9/3873 ,  G06F9/3885 ,  G06F15/7832

Abstract: Systems and apparatuses are presented relating a programmable processor comprising an execution unit that is operable to decode and execute instructions received from an instruction path and partition data stored in registers in the register file into multiple data elements, the execution unit capable of executing a plurality of different group floating-point and group integer arithmetic operations that each arithmetically operates on multiple data elements stored registers in a register file to produce a catenated result that is returned to a register in the register file, wherein the catenated result comprises a plurality of individual results, wherein the execution unit is capable of executing group data handling operations that re-arrange data elements in different ways in response to data handling instructions.

Abstract translation: 提出了一种系统和装置，其涉及包括执行单元的可编程处理器，该执行单元可操作以解码和执行从指令路径接收的指令，并将存储在寄存器堆中的寄存器中的数据分割成多个数据元素，该执行单元能够执行多个 不同的组浮点和组整数算术运算，每个算术运算在寄存器文件中的多个数据元素存储的寄存器上产生返回到寄存器文件中的寄存器的连接结果，其中，连接结果包括多个单独的结果 其中，所述执行单元能够执行响应于数据处理指令以不同方式重新布置数据元素的组数据处理操作。

公开(公告)号：US20080104375A1

公开(公告)日：2008-05-01

申请号：US11894584

申请日：2007-08-20

Applicant: Craig Hansen ,  John Moussouris ,  Alexia Massalin

Inventor： Craig Hansen ,  John Moussouris ,  Alexia Massalin

IPC: G06F9/30

CPC classification number: G06F9/3001 ,  G03F1/36 ,  G06F9/30 ,  G06F9/30007 ,  G06F9/30014 ,  G06F9/30018 ,  G06F9/30029 ,  G06F9/30032 ,  G06F9/30036 ,  G06F9/3004 ,  G06F9/30043 ,  G06F9/30054 ,  G06F9/30098 ,  G06F9/30101 ,  G06F9/30109 ,  G06F9/30112 ,  G06F9/30145 ,  G06F9/30149 ,  G06F9/3016 ,  G06F9/30167 ,  G06F9/35 ,  G06F9/383 ,  G06F9/3851 ,  G06F9/3861 ,  G06F9/3885 ,  G06F9/4484 ,  G06F9/45533 ,  G06F12/02 ,  G06F17/5068 ,  G06F17/5072 ,  G06F17/5081 ,  G06F2217/12 ,  H03M13/158 ,  H03M13/4169 ,  Y02D10/13 ,  Y02D10/26 ,  Y02D10/28 ,  Y02P90/265

Abstract: A programmable processor and method for improving the performance of processors by expanding at least two source operands, or a source and a result operand, to a width greater than the width of either the general purpose register or the data path width. The present invention provides operands which are substantially larger than the data path width of the processor by using the contents of a general purpose register to specify a memory address at which a plurality of data path widths of data can be read or written, as well as the size and shape of the operand. In addition, several instructions and apparatus for implementing these instructions are described which obtain performance advantages if the operands are not limited to the width and accessible number of general purpose registers.

Abstract translation: 一种可编程处理器和方法，用于通过将至少两个源操作数或源和结果操作数扩展到大于通用寄存器或数据路径宽度的宽度的宽度来提高处理器的性能。 本发明通过使用通用寄存器的内容来指定可以读取或写入数据的多个数据路径宽度的存储器地址，并且基本上大于处理器的数据路径宽度的操作数，以及 操作数的大小和形状。 此外，描述了用于实现这些指令的几个指令和装置，其如果操作数不限于通用寄存器的宽度和可访问数量，则获得性能优点。

公开(公告)号：US20080065860A1

公开(公告)日：2008-03-13

申请号：US11842119

申请日：2007-10-29

Applicant: Craig Hansen ,  John Moussouris

Inventor： Craig Hansen ,  John Moussouris

IPC: G06F15/78 ,  G06F9/30

CPC classification number: G06F9/30014 ,  G06F9/30018 ,  G06F9/30025 ,  G06F9/30029 ,  G06F9/30032 ,  G06F9/30036 ,  G06F9/3004 ,  G06F9/30043 ,  G06F9/30054 ,  G06F9/30087 ,  G06F9/30101 ,  G06F9/30109 ,  G06F9/30112 ,  G06F9/3012 ,  G06F9/30123 ,  G06F9/30145 ,  G06F9/3016 ,  G06F9/30167 ,  G06F9/3816 ,  G06F9/3824 ,  G06F9/383 ,  G06F9/3851 ,  G06F9/3861 ,  G06F9/3873 ,  G06F9/3885 ,  G06F15/7832

Abstract: Systems and apparatuses are presented relating a programmable processor comprising an execution unit that is operable to decode and execute instructions received from an instruction path and partition data stored in registers in the register file into multiple data elements, the execution unit capable of executing a plurality of different group floating-point and group integer arithmetic operations that each arithmetically operates on multiple data elements stored registers in a register file to produce a catenated result that is returned to a register in the register file, wherein the catenated result comprises a plurality of individual results, wherein the execution unit is capable of executing group data handling operations that re-arrange data elements in different ways in response to data handling instructions.

Abstract translation: 提出了一种系统和装置，其涉及包括执行单元的可编程处理器，该执行单元可操作以解码和执行从指令路径接收的指令，并将存储在寄存器堆中的寄存器中的数据分割成多个数据元素，该执行单元能够执行多个 不同的组浮点和组整数算术运算，每个算术运算在寄存器文件中的多个数据元素存储的寄存器上产生返回到寄存器文件中的寄存器的连接结果，其中，连接结果包括多个单独的结果 其中，所述执行单元能够执行响应于数据处理指令以不同方式重新布置数据元素的组数据处理操作。

公开(公告)号：US20040015533A1

公开(公告)日：2004-01-22

申请号：US10418113

申请日：2003-04-18

Applicant: MicroUnity Systems Engineering, Inc.

Inventor： Craig C. Hansen ,  Alexia Massalin

IPC: G06F007/38

CPC classification number: G06F9/30014 ,  G06F7/483 ,  G06F7/5443 ,  G06F9/30 ,  G06F9/30018 ,  G06F9/30025 ,  G06F9/30032 ,  G06F9/30036 ,  G06F9/30043 ,  G06F9/30145 ,  G06F9/3802 ,  G06F9/3867 ,  G06F9/3869 ,  G06F15/7832 ,  G06F15/7842 ,  G06F2207/382 ,  G06F2207/3828 ,  H04N21/2365 ,  H04N21/238 ,  H04N21/23805 ,  H04N21/4347 ,  Y02D10/13

Abstract: A multiplier array processing system which improves the utilization of the multiplier and adder array for lower-precision arithmetic is described. New instructions are defined which provide for the deployment of additional multiply and add operations as a result of a single instruction, and for the deployment of greater multiply and add operands as the symbol size is decreased.

Abstract translation: 描述了一种提高乘法器和加法器阵列对低精度运算的利用率的乘法器阵列处理系统。 定义了新的指令，它们作为单个指令的结果提供了额外的乘法和加法操作的部署，以及在符号大小减少时部署更大的乘法和加法操作数。

公开(公告)号：US5809321A

公开(公告)日：1998-09-15

申请号：US754429

申请日：1996-11-22

Applicant: Craig Hansen ,  John Moussouris

Inventor： Craig Hansen ,  John Moussouris

IPC: G06F9/30 ,  G06F9/302 ,  G06F9/308 ,  G06F9/312 ,  G06F9/315 ,  G06F9/38 ,  G06F12/08 ,  G06F12/10 ,  G06F15/78 ,  H04N5/00 ,  H04N7/24 ,  G06F9/00

CPC classification number: G06F9/3802 ,  G06F12/0875 ,  G06F12/1027 ,  G06F15/7832 ,  G06F15/7842 ,  G06F9/30 ,  G06F9/30014 ,  G06F9/30018 ,  G06F9/30025 ,  G06F9/30032 ,  G06F9/30036 ,  G06F9/3004 ,  G06F9/30043 ,  G06F9/30072 ,  G06F9/30087 ,  G06F9/30145 ,  G06F9/3867 ,  G06F9/3869 ,  H04N21/2365 ,  H04N21/238 ,  H04N21/23805 ,  H04N21/4347 ,  G06F2212/2515 ,  Y02B60/1225

Abstract: A general purpose, programmable media processor for processing and transmitting a media data stream of audio, video, radio, graphics, encryption, authentication, and networking information in real-time. The media processor incorporates an execution unit that maintains substantially peak data throughout of media data streams. The execution unit includes a dynamically partionable multi-precision arithmetic unit, programmable switch and programmable extended mathematical element. A high bandwidth external interface supplies media data streams at substantially peak rates to a general purpose register file and the multi-precision execution unit. A memory management unit, and instruction and data cache/buffers are also provided. High bandwidth memory controllers are linked in series to provide a memory channel to the general purpose, programmable media processor. The general purpose, programmable media processor is disposed in a network fabric consisting of fiber optic cable, coaxial cable and twisted pair wires to transmit, process and receive single or unified media data streams. Parallel general purpose media processors are disposed throughout the network in a distributed virtual manner to allow for multi-processor operations and sharing of resources through the network. A method for receiving, processing and transmitting media data streams over the communications fabric is also provided.

公开(公告)号：US5563535A

公开(公告)日：1996-10-08

申请号：US350131

申请日：1994-11-29

Applicant: Alan Corry ,  Robert A. Sutherland

Inventor： Alan Corry ,  Robert A. Sutherland

IPC: G06F1/03 ,  H03C3/00 ,  H03B21/00

CPC classification number: H03C3/00 ,  G06F1/0328

Abstract: A direct digital synthesizer (DDS) for generating a waveform generates a sequence of n-bit phase signals representing phase of the waveform, wherein n is an integer greater than zero. Each n-bit phase signal comprises a phase estimate signal and a phase error signal. The phase estimate signal comprises a most-significant m bits of the n-bit quantity (0

Abstract translation: 用于产生波形的直接数字合成器（DDS）产生表示波形相位的n位相位信号的序列，其中n是大于零的整数。 每个n位相位信号包括相位估计信号和相位误差信号。 相位估计信号包括n比特量（0

公开(公告)号：US5447810A

公开(公告)日：1995-09-05

申请号：US194097

申请日：1994-02-09

Applicant: Jang F. Chen ,  James A. Matthews

Inventor： Jang F. Chen ,  James A. Matthews

IPC: G03F1/00 ,  G03F7/20 ,  G03F9/00

CPC classification number: G03F7/701 ,  G03F1/36 ,  G03F7/70125 ,  G03F7/70433 ,  G03F7/70441

Abstract: In a lithographical tool utilizing off-axis illumination, masks to provide increased depth of focus and minimize CD differences between certain features is disclosed. A first mask for reducing proximity effects between isolated and densely packed features and increasing depth of focus (DOF) of isolated features is disclosed. The first mask comprises additional lines, referred to as scattering bars, disposed next to isolated edges. The bars are spaced a distance from isolated edges such that isolated and densely packed edge gradients substantially match so that proximity effects become negligible. The width of the bars set so that a maximum DOF range for the isolated feature is achieved. A second mask that is effective with quadrapole illumination only, is also disclosed. This mask "boosts" intensity levels and consequently DOF ranges for smaller square contacts so that they approximate intensity levels and DOF ranges of larger elongated contacts. Increasing the intensity levels in smaller contacts reduces critical dimension differences between variably sized contact patterns when transferred to a resist layer. The second mask comprises additional openings, referred to as anti-scattering bars, disposed about the square contact openings. The amount of separation between the edge of the smaller contact and the anti-scattering bars determines the amount of increased intensity. The width of the anti-scattering bars determines the amount of increase in DOF range. Both scattering bar and anti-scattering bars are designed to have a widths significantly less than the resolution of the exposure tool so that they do not produce a pattern during exposure of photoresist.

Abstract translation: 在利用离轴照明的光刻工具中，公开了掩模以提供增加的聚焦深度并且使特定特征之间的CD差异最小化。 公开了用于减少隔离和密集堆叠特征之间的邻近效应的第一掩模，并且增加了隔离特征的增加的焦深（DOF）。 第一掩模包括邻近隔离边缘设置的附加线，称为散射棒。 这些杆与隔离边缘间隔开一段距离，使得孤立和密集堆积的边缘梯度基本匹配，使得邻近效应变得可忽略。 条的宽度设置为使得隔离特征的最大DOF范围得以实现。 还公开了仅对四极照明有效的第二掩模。 该掩模“增加”强度水平，因此适用于较小的方形触点的DOF范围，使得它们近似于较大细长触点的强度水平和DOF范围。 增加较小触点中的强度水平可以减少转移到抗蚀剂层时可变尺寸的接触图案之间的临界尺寸差异。 第二掩模包括围绕正方形接触开口设置的称为防散射棒的附加开口。 较小触点的边缘与抗散射条之间的分离量决定了增加强度的量。 防散射条的宽度决定了DOF范围的增加量。 散射棒和防散射棒都被设计成具有明显小于曝光工具的分辨率的宽度，使得它们在光致抗蚀剂曝光期间不产生图案。

公开(公告)号：US5340700A

公开(公告)日：1994-08-23

申请号：US149122

申请日：1993-11-03

Applicant: Jang F. Chen ,  James A. Matthews

Inventor： Jang F. Chen ,  James A. Matthews

IPC: G03F7/20 ,  H01L21/027 ,  G03C5/00

CPC classification number: G03F7/70466 ,  G03F7/2022

Abstract: A method of printing a sub-resolution device feature having first and second edges spaced in close proximity to one another on a semiconductor substrate includes the steps of first depositing a radiation-sensitive material on the substrate, then providing a first mask image segment which corresponds to the first edge. The first mask image segment is then exposed with radiation using an imaging tool to produce a first pattern edge gradient. The first pattern edge gradient defines the first edge of the feature in the material.A second mask image segment is then provided corresponding to the second feature edge. This second mask image segment is exposed to radiation to produce a second pattern edge gradient which defines the second edge of the feature. Once the radiation-sensitive material has been developed, the two-dimensional feature is reproduced on the substrate.

Abstract translation: 一种打印具有在半导体衬底上彼此靠近彼此间隔开的第一和第二边缘的子分辨率器件特征的方法包括以下步骤：首先在衬底上沉积辐射敏感材料，然后提供与衬底相对应的第一掩模图像段 到第一边。 然后使用成像工具用辐射曝光第一掩模图像段以产生第一图案边缘梯度。 第一个图案边缘渐变定义材料中特征的第一个边缘。 然后对应于第二特征边缘提供第二掩模图像段。 该第二掩模图像段暴露于辐射以产生限定特征的第二边缘的第二图案边缘梯度。 一旦辐射敏感材料已经开发出来，二维特征就在基片上再现。

公开(公告)号：US5336926A

公开(公告)日：1994-08-09

申请号：US113510

申请日：1993-08-27

Applicant: James A. Matthews

Inventor： James A. Matthews

IPC: H01L29/73 ,  H01L21/331 ,  H01L21/8249 ,  H01L29/08 ,  H01L29/732 ,  H01L29/72 ,  H01L21/265

CPC classification number: H01L29/66272 ,  H01L21/8249 ,  H01L29/0826 ,  Y10S257/927

Abstract: A bipolar junction transistor (BJT) which exhibits a suppressed Kirk Effect comprises a lightly-doped n-type collector region formed above a more heavily-doped n+ layer. Directly above the collector is a p-type base which has an extrinsic region disposed laterally about an intrinsic region. An n+ emitter is positioned directly above the intrinsic base region. The BJT also includes a localized n+ region disposed directly beneath the intrinsic base region which significantly increases the current handling capabilities of the transistor.

Abstract translation: 表现出抑制Kirk效应的双极结型晶体管（BJT）包括形成在更掺杂n +层上方的轻掺杂n型集电极区域。 在集电极的正上方是p型基体，其具有在本征区域周围设置的外在区域。 n +发射极位于本征基区的正上方。 BJT还包括直接位于本征基极区域下方的局部n +区，这显着增加了晶体管的电流处理能力。