公开(公告)号：WO2012085951A1

公开(公告)日：2012-06-28

申请号：PCT/IT2010/000511

申请日：2010-12-23

Applicant: STMICROELECTRONICS S.R.L. ,  BOTTAREL, Valeria ,  RICOTTI, Giulio ,  QUAGLIA, Fabio

Inventor： BOTTAREL, Valeria ,  RICOTTI, Giulio ,  QUAGLIA, Fabio

IPC: H03K17/081 ,  H03K17/30 ,  G01S7/52 ,  B06B1/02

CPC classification number: H03K17/16 ,  H03K17/08104 ,  H03K17/30

Abstract: A low voltage isolation circuit (1) is described inserted between a connection node (HVout) to a matrix (2) of switches suitable for receiving a high voltage signal (IM) and a connection terminal (pzt) to a load (PZ) suitable for transmitting said high voltage signal (IM) to said load (PZ) of the type comprising at least one driving block (5) inserted between a first and a second voltage reference (Vss, - Vss) and comprising at least a first driving transistor (M l), inserted, in series with a first driving diode (Dl), between the first voltage reference (Vss) and a first driving central circuit node (Xc) and a second driving transistor (M2), in turn inserted, in series with a second diode (D2), between the driving central circuit node (Xc) and the second supply voltage reference (-Vss). The switch comprises an isolation block (8) connected to the connection terminal (pzt), to the connection node (HVout) and to the driving central circuit node (Xc) and comprising at least one voltage limiter block (6), a diode block (7) and a control transistor (MD), in turn connected across the diode block (7) between the connection node (HVout) to the matrix (2) of switches and the connection terminal (pzt) to the load (PZ) of the low voltage isolation switch (1) and having a control terminal (XD) connected to the driving central circuit node (Xc).

Abstract translation: 描述了一种低电压隔离电路（1），其插入到适于接收高电压信号（IM）的开关的矩阵（2）的连接节点（HVout）和适合于负载（PZ）的连接端子（pzt）之间 用于将所述高电压信号（IM）发送到包括插入在第一和第二参考电压（Vss，-Vss）之间的至少一个驱动块（5）的类型的所述负载（PZ），并且至少包括第一驱动晶体管 （M1）与第一驱动二极管（D1）串联插入在第一电压基准（Vss）和第一驱动中心电路节点（Xc）和第二驱动晶体管（M2）之间，然后插入 与驱动中心电路节点（Xc）和第二电源电压基准（-Vss）之间的第二二极管（D2）串联。 开关包括连接到连接端子（pzt）的隔离块（8），连接节点（HVout）和驱动中心电路节点（Xc），并且包括至少一个限压器块（6），二极管块 （7）和控制晶体管（MD），它们连接在连接节点（HVout）与开关矩阵（2）之间的二极管块（7）和连接端子（pzt）与负载（PZ）之间 低电压隔离开关（1）并具有连接到驱动中心电路节点（Xc）的控制端子（XD）。

公开(公告)号：WO2012085296A1

公开(公告)日：2012-06-28

申请号：PCT/EP2011/074045

申请日：2011-12-23

Applicant: STMICROELECTRONICS S.R.L. ,  PACI, Dario ,  MORELLI, Marco ,  RIVA, Caterina

Inventor： PACI, Dario ,  MORELLI, Marco ,  RIVA, Caterina

IPC: G01R33/00 ,  G01R33/09

CPC classification number: G01R33/0011 ,  B82Y25/00 ,  G01R33/093 ,  H01L43/12

Abstract: An integrated magnetoresistive device, where a substrate (17) of semiconductor material is covered, on a first surface (19), by an insulating layer (18). A magnetoresistor (26) of ferromagnetic material extends in the insulating layer and defines a sensitivity plane of the sensor. A concentrator (34) of ferromagnetic material including at least one arm (34a), extending in a transversal direction to the sensitivity plane and vertically offset to the magnetoresistor (26). In this way, magnetic flux lines directed perpendicularly to the sensitivity plane are concentrated and deflected so as to generate magnetic-field components directed in a parallel direction to the sensitivity plane.

Abstract translation: 通过绝缘层（18）在第一表面（19）上覆盖半导体材料的衬底（17）的集成磁阻器件。 铁磁材料的磁阻（26）在绝缘层中延伸并限定传感器的灵敏度平面。 铁磁材料的集中器（34）包括至少一个臂（34a），沿着横向方向延伸到灵敏度平面并垂直偏移到磁电阻（26）。 以这种方式，垂直于灵敏度平面指向的磁通线被集中和偏转，以便产生指向与灵敏平面平行的方向的磁场分量。

公开(公告)号：WO2012019768A1

公开(公告)日：2012-02-16

申请号：PCT/EP2011/004030

申请日：2011-08-11

Applicant: STMICROELECTRONICS S.R.L. ,  PAGANI, Alberto ,  GIRLANDO, Giovanni

Inventor： PAGANI, Alberto ,  GIRLANDO, Giovanni

IPC: G06K19/073

CPC classification number: G06K7/00 ,  G06K7/10178 ,  G06K19/025 ,  G06K19/072 ,  G06K19/07327 ,  G06K19/07336 ,  G06K19/07735 ,  G06K19/07756 ,  G06K19/07771 ,  G06K19/07775 ,  G06K19/07779

Abstract: The invention relates to a security system comprising at least one integrated circuit (24a) and a transceiver / transponder circuit (30), the at least one integrated circuit (24a) being provided with an antenna (36) for communicating with the transceiver / transponder circuit (30), an inhibiting element (24b, 44, 44a, 44b) being associated with the at least one integrated circuit (24a) for inhibiting communications with the transceiver / transponder circuit (30) and for securing the data contained in the at least one integrated circuit (24a). Advantageously, the inhibiting element (24b, 44, 44a, 44b) is an electromagnetic inhibiting element, the security system further comprising a coupling element (22) that is associated with the antenna (36) of the at least one integrated circuit (24a) for temporarily deactivating the electromagnetic inhibiting element (24b, 44, 44a, 44b) to allow communications between the at least one integrated circuit (24a) and the transceiver / transponder circuit (30).

Abstract translation: 本发明涉及一种包括至少一个集成电路（24a）和收发器/应答器电路（30）的安全系统，所述至少一个集成电路（24a）设置有天线（36），用于与收发器/应答器 电路（30），与所述至少一个集成电路（24a）相关联的禁止元件（24b，44,44a，44b），用于禁止与所述收发器/应答器电路（30）的通信并且用于保护包含在所述收发器/ 至少一个集成电路（24a）。 有利地，禁止元件（24b,44,44a，44b）是电磁抑制元件，所述安全系统还包括与所述至少一个集成电路（24a）的天线（36）相关联的耦合元件（22） 用于临时停用所述电磁抑制元件（24b,44,44a，44b）以允许所述至少一个集成电路（24a）与所述收发器/应答器电路（30）之间的通信。

公开(公告)号：WO2011088853A1

公开(公告)日：2011-07-28

申请号：PCT/EP2010/005927

申请日：2010-09-29

Applicant: STMICROELECTRONICS S.R.L. ,  ROSSI, Sandro ,  RICOTTI, Giulio ,  GHISU Davide Ugo ,  RICCIARDO, Antonio

Inventor： ROSSI, Sandro ,  RICOTTI, Giulio ,  GHISU Davide Ugo ,  RICCIARDO, Antonio

IPC: H03K17/06 ,  H03K17/687 ,  H03K17/74 ,  B06B1/02 ,  H03K17/0416 ,  H03K17/16

CPC classification number: H03K17/06 ,  H03K17/04163 ,  H03K17/161 ,  H03K17/6872 ,  H03K17/74

Abstract: A transmission channel (1) is described comprising at least one high voltage buffer block (4) comprising buffer transistors (MB1, MB2, MB3, MB4) and respective buffer diodes (DB1, DB2, DB3, DB4), being inserted between respective voltage references (HVP0, HVP1, HVM0, HVM1), a clamping circuit (10) being connected to a first output terminal (HVout) of the transmission channel (1), an antinoise block (6) being connected between the first output terminal (HVout) and a connection terminal (Xdcr) of the transmission channel (1); as well as a switching circuit (30) being inserted between the connection terminal (Xdcr) and a second output terminal (LVout) of the transmission channel (1). Advantageously according to the invention, the clamping circuit (10) comprises a clamping core (11), a reset circuit (20) comprising diodes (DME1, DME2, DME3, DME4 ) inserted between circuit nodes (XME1, XME2, XME3, XME4, XC1, XC2) of the high voltage buffer block (4) and of the clamping circuit (10), the circuit nodes (XME1, XME2, XME3, XME4, XC1, XC2 ) being in correspondance with conduction terminals of said transistors (MB1,MB2,MB3,MB4,MC1,MC2) comprised into the high voltage buffer block(4) and into the clamping circuit (10), and a switching circuit (30).

Abstract translation: 描述了传输通道（1），其包括至少一个包括缓冲晶体管（MB1，MB2，MB3，MB4）和相应的缓冲二极管（DB1，DB2，DB3，DB4）的高压缓冲块（4） 参考（HVP0，HVP1，HVM0，HVM1），与传输通道（1）的第一输出端子（HVout）连接的钳位电路（10），连接在第一输出端子 ）和传输信道（1）的连接终端（Xdcr）; 以及插入在传输通道（1）的连接端子（Xdcr）和第二输出端子（LVout）之间的开关电路（30）。 有利地，根据本发明，夹紧电路（10）包括夹紧芯（11），复位电路（20），其包括插入在电路节点（XME1，XME2，XME3，XME4，XME3，DME3， 高电压缓冲块（4）和钳位电路（10）的电路节点（XME1，XME2，XME3，XME4，XC1，XC2）与所述晶体管（MB1，XC1，XC2）的导通端子相对应， MB2，MB3，MB4，MC1，MC2）以及开关电路（30），其特征在于，包括高压缓冲块（4）和钳位电路（10）。

公开(公告)号：WO2011079879A1

公开(公告)日：2011-07-07

申请号：PCT/EP2010/005926

申请日：2010-09-29

Applicant: STMICROELECTRONICS S.R.L. ,  BOTTAREL, Valeria ,  RICOTTI, Giulio ,  MARABELLI, Silvia

Inventor： BOTTAREL, Valeria ,  RICOTTI, Giulio ,  MARABELLI, Silvia

IPC: H03K17/693 ,  H03K17/74 ,  H03K17/687 ,  H03K17/06 ,  B06B1/02 ,  H03K17/0812 ,  H03K17/0814

CPC classification number: H03K17/693 ,  B06B1/0215 ,  H03K17/06 ,  H03K17/08122 ,  H03K17/08142 ,  H03K17/6872 ,  H03K17/74

Abstract: A low voltage isolation circuit (1) is described inserted between an input terminal (HVout) suitable for receiving a high voltage signal (IM) and an output terminal (pzt) suitable for transmitting the high voltage signal (IM) to a load (PZ) of the type comprising at least one driving block (5) inserted between a first and a second voltage reference (Vss, -Vss) and comprising a first driving transistor (Ml), inserted between the first voltage reference (Vss) and a first driving central circuit node (Xc) and a second driving transistor (M2), in turn inserted between the driving central circuit node (Xc) and the second supply voltage reference (-Vss) as well as an isolation block (8) connected to the connection terminal (pzt), to the input terminal (HVout) and, through a protection block (9) comprising a first and a second protection transistor (MD1, MD2), being in anti-series to each other and having control terminals receiving respective complementary protection driving signals (dr1, dr2), to the driving central circuit node (Xc), the isolation block (8) comprising at least one voltage limiter block (6), a diode block (7) and a control transistor (MD), in turn connected across the diode block (7) between the input (HVout) and output (pzt) terminals of the low voltage isolation switch (1) and having a control terminal (XD) connected to the driving central circuit node (Xc) through the protection block (9), said diode block (7) comprising at least one first and one second transmission diode (DN1, DN2), connected in antiparallel, i.e. by having an anode terminal of said first diode connected to a cathode terminal of said second diode and vice versa.

Abstract translation: 描述了一种低压隔离电路（1），其插入适于接收高电压信号（IM）的输入端（HVout）和适于将高电压信号（IM）发送到负载（PZ）的输出端（pzt）之间 ）包括插入在第一和第二电压参考（Vss，-Vss）之间的至少一个驱动块（5），并且包括插入在第一电压参考（Vss）和第一电压参考（Vss）之间的第一驱动晶体管（M1） 驱动中心电路节点（Xc）和第二驱动晶体管（M2），其又插入在驱动中心电路节点（Xc）和第二电源电压参考（-Vss）之间，以及隔离块（8） 连接端子（pzt）到输入端子（HVout），并且通过包括第一和第二保护晶体管（MD1，MD2）的保护块（9）彼此反串联并且具有相应的控制端子 互补保护驾驶信号（dr1，dr 如图2所示，驱动中心电路节点（Xc），隔离块（8）包括至少一个限压器块（6），二极管块（7）和控制晶体管（MD） 在低压隔离开关（1）的输入（HVout）端子和输出端子（pzt）端子之间具有通过保护块（9）连接到驱动中心电路节点（Xc）的控制端子（XD）的块（7） ，所述二极管块（7）包括至少一个反并联连接的第一和第二传输二极管（DN1，DN2），即通过使所述第一二极管的阳极端子连接到所述第二二极管的阴极端子，反之亦然。

公开(公告)号：WO2011045083A1

公开(公告)日：2011-04-21

申请号：PCT/EP2010/006339

申请日：2010-10-18

Applicant: STMICROELECTRONICS S.R.L. ,  RICOTTI, Giulio ,  BOMPIERI, Paolo ,  ROSSI, Sandro

Inventor： RICOTTI, Giulio ,  BOMPIERI, Paolo ,  ROSSI, Sandro

IPC: H03K17/74

CPC classification number: H03K17/063

Abstract: The invention relates to a High Voltage switch configuration (10) having an input terminal (IN) which receives an input signal (Vin) to drive a load and an output terminal (OUT) which issues an output signal (Vout) to the load. Advantageously according to the invention, the High Voltage switch configuration ( 10) comprises at least a first and a second diode (D1, D2), being placed in antiseries between said input and output terminals (IN, OUT) and having a pair of corresponding terminals in common, in correspondence of a first internal circuit node (Xc1).

Abstract translation: 本发明涉及一种具有接收输入信号（Vin）以驱动负载的输入端（IN）和向负载发出输出信号（Vout）的输出端（OUT）的高压开关配置（10）。 有利地，根据本发明，高压开关配置（10）至少包括第一和第二二极管（D1，D2），放置在所述输入和输出端子（IN，OUT）之间的反电容中，并具有一对相应的 端子，对应于第一内部电路节点（Xc1）。

公开(公告)号：WO2010015388A1

公开(公告)日：2010-02-11

申请号：PCT/EP2009/005655

申请日：2009-08-05

Applicant: STMICROELECTRONICS S.R.L. ,  PAGANI, Alberto

Inventor： PAGANI, Alberto

IPC: H01L23/58 ,  G01R31/28

CPC classification number: H01L22/32 ,  G01R31/2884 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The present invention relates to a circuit architecture for the parallel supplying of power during an electric or electromagnetic testing, such as EMWS or EWS or WLBI testing, of a plurality of electronic devices (2) each integrated on a same semiconductor wafer (1) wherein the electronic devices (1) are neatly provided on the semiconductor wafer (1) through integration techniques and have edges (5) bounded by separation scribe lines (7). Advantageously according to the invention, the circuit architecture comprises: - at least one conductive grid (4), interconnecting at least one group of the electronic devices (2) and having a portion being external (14) to the devices of the group and a portion being internal (13) to the devices of the group; the external portion (14) of the conductive grid (4) being extended also along the separation scribe lines (7); the internal portion (13) being extended within at least a part of the devices of the group; interconnection pads (6) between the external portion (14) and the internal portion (13) of the conductive grid (4) being provided on at least a part of the devices of the group, the interconnection pads (6) forming, along with the internal and external portions, power supply lines which are common to different electronic devices (2) of the group.

Abstract translation: 本发明涉及用于在电子或电磁测试（例如EMWS或EWS或WLBI测试）中并行供电的电路架构，每个电子设备（2）均集成在相同的半导体晶片（1）上，其中 电子器件（1）通过积分技术整齐地设置在半导体晶片（1）上并且具有由分隔划线（7）限定的边缘（5）。 有利地，根据本发明，电路架构包括： - 至少一个导电栅格（4），其将至少一组电子设备（2）互连并且具有到该组的设备的外部（14）的部分，以及 部分是内部（13）到组的装置; 导电栅格（4）的外部部分（14）也沿着分隔划线（7）延伸; 所述内部部分（13）在所述组的装置的至少一部分内延伸; 在外部部分（14）和导电栅格（4）的内部部分（13）之间的互连焊盘（6）设置在该组的至少一部分器件上，互连焊盘（6）连同 内部和外部部分，该组的不同电子设备（2）共同的电源线。

公开(公告)号：WO2008142712A1

公开(公告)日：2008-11-27

申请号：PCT/IT2007/000357

申请日：2007-05-21

Applicant: STMICROELECTRONICS S.R.L. ,  RUSSO, Riccardo ,  TORAZZINA, Aldo

Inventor： RUSSO, Riccardo ,  TORAZZINA, Aldo

IPC: H04L12/10

CPC classification number: H04L12/10 ,  G06F1/26

Abstract: In a reliable method and a relative circuit for monitoring the powering of a remote device through a LAN it is not necessary to generate an extra biasing voltage higher than the DC power supply voltage. As in known power distribution systems, the DC voltage used for supplying the remote device is applied to the LAN line and at the same time an AC voltage is applied to the same line for monitoring whether the remote device is connected or not to the LAN line. However, differently from prior techniques, the DC voltage is applied to a first or "high" terminal and the AC voltage is applied to the other or "low" terminal of the LAN line through a decoupling capacitor. This arrangement makes possible to supply the remote device with the largest possible DC voltage compatible with a fully integrated AC signal generator, disconnection detector and PSE controller and enhances the reliability of recognition of whether the powered device is connected to or disconnected from the LAN line.

Abstract translation: 在通过LAN监视远程设备的可靠方法和相关电路中，不需要产生高于直流电源电压的额外偏置电压。 如在已知的配电系统中，用于供应远程设备的直流电压被施加到LAN线路，同时将AC电压施加到同一线路上，用于监视远程设备是否连接到LAN线路 。 然而，与现有技术不同，DC电压被施加到第一或“高”端子，并且AC电压通过去耦电容器施加到LAN线路的另一个或“低”端。 这种布置使远程设备能够与完全集成的AC信号发生器，断开检测器和PSE控制器兼容的可能的最大直流电压提供给远程设备，并增强了识别被动设备是否连接到LAN线路或从LAN线路断开的可靠性。

公开(公告)号：WO2008026228A1

公开(公告)日：2008-03-06

申请号：PCT/IT2006/000629

申请日：2006-08-28

Applicant: STMICROELECTRONICS S.R.L. ,  ZAMPROGNO, Marco ,  CONFALONIERI, Pierangelo ,  MINUTI, Alberto

Inventor： ZAMPROGNO, Marco ,  CONFALONIERI, Pierangelo ,  MINUTI, Alberto

IPC: H03F3/00 ,  H03F3/45

CPC classification number: H03F3/005 ,  H03F3/45192 ,  H03F2203/45028 ,  H03F2203/45138 ,  H03F2203/45396 ,  H03F2203/45534 ,  H03F2203/45726

Abstract: An electrical circuit (1) for conversion from differential to single-ended is described, comprising: a differential amplifier stage (2) having a first (IN+) and a second (IN") input; a first (5) and a different second charging circuit (6) of the differential stage that can be operatively coupled, respectively, with an output (OUT*) of the conversion circuit (1) and with an auxiliary output (AUXOUT*). The circuit also comprises a first (7) and a second (8) buffer circuit each functionally arranged between one of said outputs\and between one of said charging circuits. The buffer circuits being configured so as to minimise a difference between the relative impedances seen towards said outputs (OUT*, AUXOUT*).

Abstract translation: 描述了用于从差分转换为单端的电路（1），包括：具有第一（IN +）和第二（IN“）输入的差分放大器级（2） 差动级的第一（5）和不同的第二充电电路（6），其可以分别与转换电路（1）的输出（OUT *）和辅助输出（AUXOUT *）可操作地耦合。 该电路还包括第一（7）和第二（8）缓冲电路，每个功能性地布置在所述输出端之一之间和所述充电电路之一之间。 缓冲器电路被配置为使得朝着所述输出（OUT *，AUXOUT *）看到的相对阻抗之间的差异最小化。

公开(公告)号：WO2008018094A1

公开(公告)日：2008-02-14

申请号：PCT/IT2006/000606

申请日：2006-08-07

Applicant: STMICROELECTRONICS S.R.L. ,  FAGNANI Mauro ,  BARTOLO Vincenzo ,  ADRAGNA Claudio

Inventor： FAGNANI Mauro ,  BARTOLO Vincenzo ,  ADRAGNA Claudio

IPC: G05F1/70 ,  H02M1/00

CPC classification number: G05F1/70

Abstract: Herein described is a control device of a device for the correction of the power factor in forced switching power supplies; said device for the correction of the power factor comprises a converter (20) and said control device (1) is coupled to the converter to obtain from an alternating input line voltage (Vin) a regulated output voltage (Vout) . The control device (1) comprises generating means (421-423) associated to a capacitor (Cf f) for generating a signal (Vff) representative of the root-mean- square value of the alternating line voltage; the generating means (421-424) are associated to means for discharging (Rf f) said capacitor. The control device comprises further means for discharging (Ml, COMPl, Cl; Ml 6, COMPI 1, CI 1; M50, COMP22, C0MP33, Cint) the capacitor (Cf f) suitable for discharging said capacitor when the signal (Vff) representative of the root-mean- square value of the alternating line voltage goes below a given value (VCl, VCI 1, Vint) .

Abstract translation: 这里描述了用于校正强制开关电源中的功率因数的装置的控制装置; 所述用于校正功率因数的装置包括转换器（20），并且所述控制装置（1）耦合到转换器以从交流输入线电压（Vin）获得调节输出电压（Vout）。 控制装置（1）包括与电容器（Cf f）相关联的产生装置（421-423），用于产生表示交流线路电压的均方根值的信号（Vff）; 发生装置（421-424）与用于放电（Rf f）所述电容器的装置相关联。 当信号（Vff）代表时，控制装置还包括用于放电（M1，COMP1，C1; M116，COMP1,1C1; M50，COMP22，C0MP33，Cint）适合于放电所述电容器的电容器（Cf f） 的交流线电压的均方根值低于给定值（VCl，VCI 1，Vint）。