公开(公告)号：JP2011029606A

公开(公告)日：2011-02-10

申请号：JP2010127920

申请日：2010-06-03

Applicant: Stmicroelectronics (Rousset) Sas ,  エスティマイクロエレクトロニクス(ルッセ)エスエーエスStmicroelectronics(Rousset)Sas

Inventor： RIVERO CHRISTIAN ,  FORNARA PASCAL

IPC: H01L35/30 ,  H01L21/822 ,  H01L27/04 ,  H01L35/14 ,  H01L35/16 ,  H01L35/28 ,  H02N11/00

CPC classification number: H01L35/30 ,  H01L27/16 ,  H01L35/00 ,  H01L37/00

Abstract: PROBLEM TO BE SOLVED: To provide an integrated circuit including a means which includes producing at least one temperature gradient in at least one region of an integrated circuit resulting from a flow of an electric current in at least a part of the integrated circuit during operation of the integrated circuit, and producing electrical energy through that temperature gradient. SOLUTION: The integrated circuit includes: at least one region RG containing at least one thermoelectric material MTH, which is configured to be subjected to at least one temperature gradient produced by a flow of an electric current in at least parts PSTA, PSTB of the integrated circuit during operation of the integrated circuit; and an electric conduction outputting means connected to that region RG, which transfers electric energy produced from the thermoelectric material MTH. COPYRIGHT: (C)2011,JPO&INPIT

Abstract translation: 要解决的问题：提供一种集成电路，其包括在至少一部分集成电路中产生由集成电路的至少一个区域中产生至少一个温度梯度的装置， 在集成电路运行期间，通过该温度梯度产生电能。 集成电路包括：至少一个包含至少一个热电材料MTH的区域RG，其被配置为经受至少一部分PSTA，PSTB中的电流流产生的至少一个温度梯度 的集成电路运行期间的集成电路; 以及连接到该区域RG的导电输出装置，该区域传送从热电材料MTH产生的电能。 版权所有（C）2011，JPO＆INPIT

公开(公告)号：JP2011018891A

公开(公告)日：2011-01-27

申请号：JP2010127892

申请日：2010-06-03

Applicant: Stmicroelectronics (Rousset) Sas ,  Univ Aix-Marseille 1 Provence ,  エスティマイクロエレクトロニクス(ルッセ)エスエーエスStmicroelectronics(Rousset)Sas ,  ユニベルシテ エクス−マルセイユ 1 プロバンスUniversite Aix−Marseille 1 Provence

Inventor： SCHWARZ CHRISTIAN ,  MONSERIE CHRISTOPHE ,  DELALLEAU JULIEN

IPC: H01L41/113 ,  H01L41/18 ,  H01L41/22 ,  H01L41/24 ,  H02N2/00

CPC classification number: H01L41/25 ,  H01L27/20 ,  H01L41/113 ,  H02N2/183

Abstract: PROBLEM TO BE SOLVED: To provide a method of generating electrical energy in an integrated circuit.SOLUTION: The integrated circuit includes at least one three-dimensional enclosed space CG made within the integrated circuit CI and containing at least one piezoelectric element EPZI, at least one object BL housed in a free manner in the three-dimensional enclosed space CG or each three-dimensional enclosed space CG, and an electrically conducting output means MSE coupled to the piezoelectric element EPZI and configured to deliver electrical energy resulting from at least one impact between the object BLi and the piezoelectric element EPZI during a relative motion of the object BL and the corresponding enclosed space CG.

Abstract translation: 要解决的问题：提供一种在集成电路中产生电能的方法。解决方案：集成电路包括至少一个在集成电路CI内制成的三维封闭空间CG，至少包含一个压电元件EPZI 一个物体BL以自由的方式容纳在三维封闭空间CG或每个三维封闭空间CG中，以及耦合到压电元件EPZI并被配置为传递由至少一个冲击产生的电能的导电输出装置MSE 在物体BL和相应的封闭空间CG的相对运动期间在物体BLi和压电元件EPZI之间。

公开(公告)号：JP2011003189A

公开(公告)日：2011-01-06

申请号：JP2010134405

申请日：2010-06-11

Applicant: Stmicroelectronics (Rousset) Sas ,  エスティマイクロエレクトロニクス(ルッセ)エスエーエスStmicroelectronics(Rousset)Sas

Inventor： LISART MATHIEU ,  MERCIER JULIEN

IPC: G06F12/16

CPC classification number: G06F11/1032 ,  G11C7/24

Abstract: PROBLEM TO BE SOLVED: To detect an attack by fault injection on a memory device.SOLUTION: A memory device includes a fault injection attack detection means including a group of memory planes (PM) each storing a block (BL) having data bits and m-parity bits, and a means (ML) for reading each bit of the block, and a verification means for performing a parity check based on the read value of each data bit and the read value of each parity bit at the time of reading the block. The memory plane (PM) includes reference memory cells disposed between the memory cells of the group to form separate packets (PQ) of m-memory cells. Each reference memory cell stores a reference bit changed with a reference value during the fault injection attack. Each packet of m-memory cells stores m-bits of the block associated with different parities.

Abstract translation: 要解决的问题：检测存储设备上的故障注入的攻击。解决方案：存储设备包括故障注入攻击检测装置，其包括一组存储器平面（PM），每个存储器平面（PM）存储具有数据位和m 极性位和用于读取块的每个位的装置（ML），以及用于基于每个数据位的读取值和读取时的每个奇偶校验位的读取值执行奇偶校验的校验装置 块。 存储器平面（PM）包括设置在组的存储器单元之间的参考存储单元，以形成m个存储单元的单独分组（PQ）。 每个参考存储单元存储在故障注入攻击期间用参考值改变的参考位。 m个存储器单元的每个分组存储与不同奇偶校验相关联的块的m位。