公开(公告)号：JP2010245548A

公开(公告)日：2010-10-28

申请号：JP2010137515

申请日：2010-06-16

Applicant: Asm America Inc ,  Imec ,  アイメックImec ,  エイエスエム・アメリカ・インコーポレイテッドAsm America Inc.

Inventor： CHEN JERRY ,  WILMAN TSAI ,  CAYMAX MATTY ,  MAES JAN-WILLEM

IPC: H01L29/78 ,  C23C16/02 ,  C23C16/30 ,  C23C16/34 ,  C23C16/40 ,  C23C16/44 ,  C23C16/455 ,  C23C16/56 ,  H01L21/28 ,  H01L21/314 ,  H01L21/316 ,  H01L21/318 ,  H01L21/471 ,  H01L21/8242 ,  H01L27/108 ,  H01L29/51 ,  H01L29/772

CPC classification number: H01L21/28194 ,  C23C16/0218 ,  C23C16/308 ,  C23C16/345 ,  C23C16/405 ,  C23C16/45525 ,  C23C16/45529 ,  C23C16/45531 ,  C23C16/45536 ,  C23C16/56 ,  H01L21/28185 ,  H01L21/28202 ,  H01L21/3141 ,  H01L21/3144 ,  H01L21/31604 ,  H01L21/31645 ,  H01L21/318 ,  H01L21/3185 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L2924/0002 ,  H01L2924/00

Abstract: PROBLEM TO BE SOLVED: To fabricate a MOS transistor that improves electric characteristics by avoiding formation of an interface layer with a gate electrode layer. SOLUTION: The MOS transistor includes a gate electrode, a channel region having a top surface of a gate electrode base, and a dielectric stack 37 interposed between the gate electrode and the top surface of the channel region. The dielectric stack comprises a high-k dielectric layer 31 comprising at least a high-k material, a dielectric layer comprising at least silicon and nitrogen, and an intermediate layer disposed between the high-k dielectric layer and the dielectric layer. The intermediate layer includes the high-k material, silicon, and nitrogen. The gate electrode is made of polysilicon or polysilicon germanium. COPYRIGHT: (C)2011,JPO&INPIT

Abstract translation: 要解决的问题：制造通过避免与栅电极层形成界面层来改善电特性的MOS晶体管。 解决方案：MOS晶体管包括栅电极，具有栅电极基底的顶表面的沟道区和插入在栅电极和沟道区的顶表面之间的电介质叠层37。 电介质堆叠包括至少包括高k材料的高k电介质层31，至少包含硅和氮的电介质层，以及设置在高k电介质层和电介质层之间的中间层。 中间层包括高k材料，硅和氮。 栅电极由多晶硅或多晶硅锗制成。 版权所有（C）2011，JPO＆INPIT

公开(公告)号：JP5214667B2

公开(公告)日：2013-06-19

申请号：JP2010137515

申请日：2010-06-16

Applicant: アイメックImec ,  エイエスエム・アメリカ・インコーポレイテッドAsm America Inc.

Inventor： ジェリー・チェン ,  ツァイ・ウィルマン ,  マッティ・カイマックス ,  ヤン−ウィレム・メース

IPC: H01L21/336 ,  C23C16/02 ,  C23C16/30 ,  C23C16/34 ,  C23C16/40 ,  C23C16/44 ,  C23C16/455 ,  C23C16/56 ,  H01L21/28 ,  H01L21/314 ,  H01L21/316 ,  H01L21/318 ,  H01L21/471 ,  H01L21/8242 ,  H01L27/108 ,  H01L29/51 ,  H01L29/772 ,  H01L29/78

CPC classification number: H01L21/28194 ,  C23C16/0218 ,  C23C16/308 ,  C23C16/345 ,  C23C16/405 ,  C23C16/45525 ,  C23C16/45529 ,  C23C16/45531 ,  C23C16/45536 ,  C23C16/56 ,  H01L21/28185 ,  H01L21/28202 ,  H01L21/3141 ,  H01L21/3144 ,  H01L21/31604 ,  H01L21/31645 ,  H01L21/318 ,  H01L21/3185 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L2924/0002 ,  H01L2924/00

公开(公告)号：JP2012231165A

公开(公告)日：2012-11-22

申请号：JP2012153053

申请日：2012-07-06

Applicant: Asm America Inc ,  エーエスエム アメリカ インコーポレイテッド

Inventor： MATTHIAS BAUER

IPC: H01L21/20 ,  C30B1/00 ,  H01L20060101 ,  H01L21/02 ,  H01L21/265 ,  H01L21/76 ,  H01L27/12

CPC classification number: H01L21/02381 ,  H01L21/02488 ,  H01L21/02499 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02667 ,  H01L21/26506 ,  H01L21/84

Abstract: PROBLEM TO BE SOLVED: To provide methods for producing SiGe-on-insulator structures and for forming strain-relaxed SiGe layers on silicon while minimizing defects.SOLUTION: Amorphous SiGe layers 600 are deposited on at least one monolayer of a dopant by CVD from trisilane and GeH. The amorphous SiGe layers 600 are recrystallized over silicon by melt or solid phase epitaxy (SPE) processes. The melt processes preferably also cause diffusion of germanium to dilute the overall germanium content and essentially consume silicon 500 overlying an insulator. The SPE process can be conducted with or without diffusion of germanium into the underlying silicon 500, and so is applicable to SOI as well as conventional semiconductor substrates.

Abstract translation: 要解决的问题：提供用于制造绝缘体上硅结构并在硅上形成应变松弛SiGe层的方法，同时使缺陷最小化。 解决方案：非晶SiGe层600通过CVD从丙硅烷和GeH 4 沉积在掺杂剂的至少一个单层上。 非晶SiGe层600通过熔融或固相外延（SPE）工艺在硅上重结晶。 熔融方法优选还引起锗的扩散以稀释总锗含量，并且基本上消耗覆盖在绝缘体上的硅500。 SPE工艺可以在有或没有锗扩散到下面的硅500的情况下进行，因此也适用于SOI以及常规的半导体衬底。 版权所有（C）2013，JPO＆INPIT

公开(公告)号：JP2012089863A

公开(公告)日：2012-05-10

申请号：JP2011265435

申请日：2011-12-05

Applicant: Asm America Inc ,  エーエスエム アメリカ インコーポレイテッド

Inventor： MOHITH VERGHESE ,  SHERO ERIC ,  BAVIC DACO ,  HERBERT TERHORST ,  MARKO PEUSSA ,  YANG MIN

IPC: H01L21/205 ,  C23C16/458

CPC classification number: H01L21/68785 ,  C23C16/4408 ,  C23C16/455 ,  C23C16/45517 ,  C23C16/45525 ,  C23C16/45544 ,  C23C16/45561 ,  C23C16/45563 ,  C23C16/45582 ,  C23C16/45587 ,  C23C16/45591 ,  C23C16/458 ,  C23C16/4582 ,  C23C16/4583 ,  C23C16/4586 ,  C30B35/00 ,  H01L21/67236 ,  H01L21/68714 ,  H01L21/68742

Abstract: PROBLEM TO BE SOLVED: To provide an atomic layer deposition (ALD) thin film deposition apparatus in which the amount of remaining reaction substance is small during a purging period succeeding to a reaction substance pulse.SOLUTION: The apparatus is configured to deposit a thin film on a wafer mounted within a space defined in a deposition chamber and includes a gas inlet that is in communication with the space, a sealing portion 604 that includes a sealing surface 605, the deposition chamber and a susceptor 602. The susceptor 602 is configured to support the wafer within the space. The susceptor 602 is configured to move vertically with respect to the deposition chamber between a first position in which the susceptor 602 seals against the sealing surface 605 and a second, lower position in which the susceptor 602 no longer seals against the sealing surface 605. In the first position, a vertical distance between the interface between the sealing surface 605 and the susceptor 602 and the top face of the wafer positioned on the susceptor 602 is less than about 2 millimeters.

Abstract translation: 解决的问题：提供一种原子层沉积（ALD）薄膜沉积装置，其中在反应物质脉冲之后的清洗期间剩余反应物质的量少。 解决方案：该装置被配置为将薄膜沉积在安装在沉积室中限定的空间内的晶片上，并且包括与该空间连通的气体入口，包括密封表面605的密封部分604， 沉积室和基座602.基座602被配置为在该空间内支撑晶片。 基座602被配置为相对于沉积室垂直移动，其中基座602密封在密封表面605的第一位置和基座602不再密封到密封表面605的第二下部位置。在 第一位置，密封表面605和基座602之间的界面与位于基座602上的晶片的顶面之间的垂直距离小于约2毫米。 版权所有（C）2012，JPO＆INPIT

公开(公告)号：JP4647311B2

公开(公告)日：2011-03-09

申请号：JP2004557681

申请日：2003-12-09

Applicant: アイメックImec ,  エイエスエム・アメリカ・インコーポレイテッドAsm America Inc.

Inventor： ジェリー・チェン ,  ツァイ・ウィルマン ,  マッティ・カイマックス ,  ヤン−ウィレム・メース

IPC: H01L21/318 ,  C23C16/02 ,  C23C16/30 ,  C23C16/34 ,  C23C16/40 ,  C23C16/44 ,  C23C16/455 ,  C23C16/56 ,  H01L21/28 ,  H01L21/314 ,  H01L21/316 ,  H01L21/471 ,  H01L21/8242 ,  H01L27/108 ,  H01L29/51 ,  H01L29/772 ,  H01L29/78

CPC classification number: H01L21/28194 ,  C23C16/0218 ,  C23C16/308 ,  C23C16/345 ,  C23C16/405 ,  C23C16/45525 ,  C23C16/45529 ,  C23C16/45531 ,  C23C16/45536 ,  C23C16/56 ,  H01L21/28185 ,  H01L21/28202 ,  H01L21/3141 ,  H01L21/3144 ,  H01L21/31604 ,  H01L21/31645 ,  H01L21/318 ,  H01L21/3185 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L2924/0002 ,  H01L2924/00

公开(公告)号：JP2008235888A

公开(公告)日：2008-10-02

申请号：JP2008063701

申请日：2008-03-13

Applicant: Asm America Inc ,  エーエスエム アメリカ インコーポレイテッド

Inventor： MACHKAOUTSAN VLADIMIR ,  ERNST H A GURANNEMAN

IPC: H01L21/28 ,  H01L21/3205 ,  H01L21/336 ,  H01L23/52 ,  H01L29/78

CPC classification number: H01L21/28518

Abstract: PROBLEM TO BE SOLVED: To provide a highly thermally stable metal silicide, and to provide method that utilizing the metal silicide in semiconductor processing.
SOLUTION: A metal silicide 34a is, preferably, a nickel silicide formed by the reaction of nickel with substitutionally carbon-doped single-crystal silicon which has about 2 atomic% or higher of substitutional carbon. Contrary to expectation, the metal silicide 34a is stable to temperatures of about 900°C and higher, and its sheet resistance is substantially unaffected by exposure to high temperatures. The metal silicide is compatible with subsequent high-temperature processing steps, including reflow annealing of BPSG 42.
COPYRIGHT: (C)2009,JPO&INPIT

Abstract translation: 要解决的问题：提供高度热稳定的金属硅化物，并提供在半导体加工中利用金属硅化物的方法。 解决方案：金属硅化物34a优选是通过镍与具有约2原子％或更高的取代碳的替代碳掺杂单晶硅的反应形成的硅化镍。 与预期相反，金属硅化物34a对于约900℃和更高的温度是稳定的，并且其薄层电阻基本上不受暴露于高温的影响。 金属硅化物与随后的高温加工步骤兼容，包括BPSG 42的回流退火。版权所有（C）2009，JPO＆INPIT

公开(公告)号：JP2008098668A

公开(公告)日：2008-04-24

申请号：JP2007328687

申请日：2007-12-20

Applicant: Asm America Inc ,  エーエスエム アメリカ インコーポレイテッド

Inventor： TODD MICHAEL A

IPC: C23C16/24 ,  H01L21/205 ,  C23C16/02 ,  C23C16/42 ,  C30B25/02 ,  H01L21/20 ,  H01L21/28 ,  H01L21/285 ,  H01L21/316 ,  H01L21/331 ,  H01L21/337 ,  H01L21/425 ,  H01L21/469 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/51 ,  H01L29/737 ,  H01L29/78 ,  H01L31/18 ,  H01L31/20

CPC classification number: C23C16/0272 ,  B82Y10/00 ,  B82Y30/00 ,  C23C16/22 ,  C23C16/24 ,  C23C16/30 ,  C23C16/308 ,  C23C16/325 ,  C23C16/345 ,  C23C16/36 ,  C23C16/56 ,  C30B25/02 ,  C30B29/06 ,  H01L21/02422 ,  H01L21/0243 ,  H01L21/0245 ,  H01L21/0251 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/02576 ,  H01L21/02579 ,  H01L21/02592 ,  H01L21/02595 ,  H01L21/02598 ,  H01L21/0262 ,  H01L21/02667 ,  H01L21/2257 ,  H01L21/28035 ,  H01L21/28044 ,  H01L21/28194 ,  H01L21/28525 ,  H01L21/28556 ,  H01L21/3185 ,  H01L21/32055 ,  H01L28/84 ,  H01L29/127 ,  H01L29/51 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66181 ,  H01L29/66242 ,  H01L31/1804 ,  H01L31/182 ,  H01L31/202 ,  Y02E10/546 ,  Y02E10/547 ,  Y02P70/521 ,  Y10S438/933

Abstract: PROBLEM TO BE SOLVED: To provide a method of forming a gradient film containing SiGe. SOLUTION: A step of preparing a substrate arranged in a CVD chamber, and a step of depositing a gradient film containing SiGe on the substrate by thermal CVD using a deposition gas which contains a predetermined amount of trisilane and a germanium precursor and makes the predetermined amount change while deposition are included. COPYRIGHT: (C)2008,JPO&INPIT

Abstract translation: 待解决的问题：提供一种形成含有SiGe的梯度膜的方法。 解决方案：制备布置在CVD室中的衬底的步骤，以及通过使用含有预定量的硅烷和锗前体的沉积气体通过热CVD在衬底上沉积含有SiGe的梯度膜的步骤， 在包括沉积时预定量改变。 版权所有（C）2008，JPO＆INPIT

公开(公告)号：JP2008091320A

公开(公告)日：2008-04-17

申请号：JP2007159858

申请日：2007-06-18

Applicant: Asm America Inc ,  エーエスエム アメリカ インコーポレイテッド

Inventor： HARO ROBERT C ,  HARVEY ELLIS G

IPC: H05B3/02 ,  C23C16/46 ,  H01L21/205 ,  H05B3/44

CPC classification number: H01R11/26 ,  C23C16/481 ,  F16B41/002 ,  F16B43/00 ,  H01L21/67115 ,  H01R4/302 ,  H01R11/12 ,  H05B3/0047

Abstract: PROBLEM TO BE SOLVED: To provide a fastener for screwing a lamp inside a semiconductor processing reactor with easy screw exchanges but with a screw not inadvertently coming off. SOLUTION: The fastener 38 of a captured type capable of attaching a lamp inside a radiantly heated semiconductor processing reactor, is captured within an eyelet terminal 32 on each end of the lamp, thereby rotatably securing the fastener 38 to the lamp. The eyelet terminal 32 may have a threaded aperture which screws into a threaded part of the fastener 38. Alternatively, the terminal may be adapted with a tab, a conductor extension or a housing assembly which fold over the top of a fastener inserted through the terminal. In another embodiment, the terminal may be adapted with notched projections which engage a circular dovetail in the fastener inserted through the terminal. COPYRIGHT: (C)2008,JPO&INPIT

Abstract translation: 要解决的问题：提供一种紧固件，用于在具有容易的螺旋交换但是不会无意地脱落的螺钉的情况下将灯具旋入半导体处理反应器内部。 解决方案：将能够将灯附接到辐射加热的半导体处理反应器内的捕获型紧固件38被捕获在灯的每个端部上的孔眼端子32内，从而将紧固件38可旋转地固定到灯。 孔眼终端32可以具有螺纹孔，螺纹孔螺钉到紧固件38的螺纹部分中。或者，端子可以适配于突出部，导体延伸部或壳体组件，所述突出部，导体延伸部或壳体组件折叠穿过终端插入的紧固件的顶部 。 在另一个实施例中，端子可以适合于插入穿过端子的紧固件中接合圆形燕尾的凹口突起。 版权所有（C）2008，JPO＆INPIT

公开(公告)号：JP2006216955A

公开(公告)日：2006-08-17

申请号：JP2006025710

申请日：2006-02-02

Applicant: Asm America Inc ,  エーエスエム アメリカ インコーポレイテッド

Inventor： BAUER MATTHIAS

IPC: H01L21/205 ,  C23C16/24 ,  H01L29/78

CPC classification number: H01L29/7848 ,  C23C16/04 ,  C23C16/22 ,  C23C16/24 ,  C23C16/32 ,  C23C16/325 ,  C23C16/45512 ,  C30B25/02 ,  C30B29/06 ,  H01L21/02381 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/02576 ,  H01L21/02579 ,  H01L21/0262 ,  H01L21/02636 ,  H01L21/02639 ,  H01L21/32056 ,  H01L21/3215 ,  H01L29/165 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7834

Abstract: PROBLEM TO BE SOLVED: To provide a deposition method of electrically active doped Si-containing crystalline films. SOLUTION: The method of manufacturing the Si-containing films that contain relatively high levels of group III or group V dopants involves chemical vapor deposition using trisilane and a dopant precursor. Extremely high levels of substitutional incorporation may be obtained, including crystalline silicon films that contain at least about 3×10 20 atoms cm -3 of an electrically active dopant. Substitutionally doped Si-containing films may be selectively deposited onto the crystalline surfaces of mixed substrates by introducing an etchant gas during deposition. COPYRIGHT: (C)2006,JPO&NCIPI

Abstract translation: 要解决的问题：提供电活性掺杂的含Si晶体膜的沉积方法。 解决方案：制备含有相对高含量的III族或V族掺杂剂的含Si膜的方法涉及使用丙硅烷和掺杂剂前体的化学气相沉积。 可以获得非常高的取代掺入水平，包括含有电活性掺杂剂的至少约3×10 3原子的结晶硅膜。 通过在沉积期间引入蚀刻剂气体，可将选择性地掺杂的含Si薄膜选择性地沉积在混合基板的晶体表面上。 版权所有（C）2006，JPO＆NCIPI

公开(公告)号：JP2011228724A

公开(公告)日：2011-11-10

申请号：JP2011127316

申请日：2011-06-07

Applicant: Asm America Inc ,  エーエスエム アメリカ インコーポレイテッド

Inventor： TODD MICHAEL A ,  MARK R HAWKINS

IPC: C23C16/24 ,  H01L21/205 ,  C23C16/02 ,  C23C16/42 ,  C30B25/02 ,  H01L21/20 ,  H01L21/28 ,  H01L21/285 ,  H01L21/316 ,  H01L21/318 ,  H01L21/331 ,  H01L21/337 ,  H01L21/425 ,  H01L21/469 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/51 ,  H01L29/737 ,  H01L29/78 ,  H01L31/18 ,  H01L31/20

CPC classification number: C23C16/0272 ,  B82Y10/00 ,  B82Y30/00 ,  C23C16/22 ,  C23C16/24 ,  C23C16/30 ,  C23C16/308 ,  C23C16/325 ,  C23C16/345 ,  C23C16/36 ,  C23C16/56 ,  C30B25/02 ,  C30B29/06 ,  H01L21/02422 ,  H01L21/0243 ,  H01L21/0245 ,  H01L21/0251 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/02576 ,  H01L21/02579 ,  H01L21/02592 ,  H01L21/02595 ,  H01L21/02598 ,  H01L21/0262 ,  H01L21/02667 ,  H01L21/2257 ,  H01L21/28035 ,  H01L21/28044 ,  H01L21/28194 ,  H01L21/28525 ,  H01L21/28556 ,  H01L21/3185 ,  H01L21/32055 ,  H01L28/84 ,  H01L29/127 ,  H01L29/51 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66181 ,  H01L29/66242 ,  H01L31/1804 ,  H01L31/182 ,  H01L31/202 ,  Y02E10/546 ,  Y02E10/547 ,  Y02P70/521 ,  Y10S438/933

Abstract: PROBLEM TO BE SOLVED: To provide a method of depositing highly uniform Si or SiGe over the surface of a substrate.SOLUTION: In a chemical vapor deposition process, a chemical precursor that enables thin films to be deposited in or near a limited conveyance area is utilized. By this process, it is possible to produce a film both higher in deposition velocity and more uniform in composition and thickness than a film prepared by using a conventional chemical precursor. In a preferable embodiment, Si-containing thin films useful to the semiconductor industry for various purposes including transistor gate electrodes can be deposited by using trisilane.

Abstract translation: 要解决的问题：提供在衬底的表面上沉积高度均匀的Si或SiGe的方法。 解决方案：在化学气相沉积工艺中，利用能够使薄膜沉积在有限输送区域内或附近的化学前体。 通过该方法，可以制备比通过使用常规化学前体制备的膜更高的沉积速度并且组成和厚度更均匀的膜。 在优选的实施方案中，可以使用丙硅烷，沉积可用于包括晶体管栅电极在内的各种用途的半导体工业的含Si薄膜。 版权所有（C）2012，JPO＆INPIT