公开(公告)号：WO2006126092A2

公开(公告)日：2006-11-30

申请号：PCT/IB2006/001468

申请日：2006-05-26

Applicant: ATI TECHNOLOGIES, INC. ,  ATI INTERNATIONAL S.R.L. ,  CAMPBELL, Jon ,  RIBBLE, Maurice

Inventor： CAMPBELL, Jon ,  RIBBLE, Maurice

IPC: G06T1/20

CPC classification number: G06F15/16 ,  G06T1/20 ,  G06T15/005

Abstract: Systems and methods are provided for processing data. The systems and methods include multiple processors that each couple to receive commands and data, where the commands and/or data correspond to frames of video that include multiple pixels. An interlink module is coupled to receive processed data corresponding to the frames from each of the processors. The interlink module divides a first frame into multiple frame portions by dividing pixels of the first frame using at least one balance point. The interlink module dynamically determines a position for the balance point that minimizes differences between the workload of the processors during processing of commands and/or data of one or more subsequent frames.

Abstract translation: 提供了处理数据的系统和方法。 系统和方法包括每个耦合以接收命令和数据的多个处理器，其中命令和/或数据对应于包括多个像素的视频帧。 互连模块被耦合以接收对应于来自每个处理器的帧的处理数据。 互连模块通过使用至少一个平衡点划分第一帧的像素来将第一帧划分成多个帧部分。 互连模块动态地确定在处理命令和/或一个或多个后续帧的数据期间最小化处理器的工作量之间的平衡点的位置。

公开(公告)号：EP1688907A2

公开(公告)日：2006-08-09

申请号：EP06075947.9

申请日：2000-06-15

Applicant: ATI International S.R.L

Inventor： Callway, Edward G.

IPC: G09G5/36 ,  G09G5/02

CPC classification number: G09G5/399 ,  G06F3/1438 ,  G09G5/003 ,  G09G5/06 ,  G09G5/36 ,  G09G5/363 ,  G09G2320/0233 ,  G09G2320/0271 ,  G09G2320/0693 ,  G09G2340/12 ,  G09G2360/18

Abstract: Multiple Video Graphic Adapters (VGAs) are used to render video data to a common port. In one embodiment, each VGA will render an entire frame of video and provide it to the output port through a switch. The next adjacent frame will be calculated by a separate VGA and provided to an output port through the switch. A voltage adjustment is made to a digital-to-analog converter(DAC) of at least one of the VGAs in order to correlate the video-out voltages being provided by the VGAs. This correlation assures that the colour being viewed on the screen is uniform regardless of which VGA is providing the signal. A dummy switch receives the video-output from each of the VGAs. When a VGA is not providing information to the output port, the dummy switch can be selected to provide the video-output of the selected VGA a resistance path which matches the resistance at the video port. This allows the video graphics controller to maintain a constant thermal state.

Abstract translation: 多视频图形适配器（VGA）用于将视频数据呈现给公共端口。 在一个实施例中，每个VGA将呈现整个视频帧，并通过交换机将其提供给输出端口。 下一个相邻的帧将通过单独的VGA计算，并通过交换机提供给输出端口。 对VGA中的至少一个的数模转换器（DAC）进行电压调整，以便将由VGA提供的视频输出电压相关联。 这种相关性确保在屏幕上观看的颜色是均匀的，而不管哪个VGA提供信号。 虚拟开关从每个VGA接收视频输出。 当VGA不向输出端口提供信息时，可以选择虚拟开关以提供所选VGA的视频输出与视频端口上的电阻匹配的电阻路径。 这允许视频图形控制器保持恒定的热状态。

公开(公告)号：EP0987850B1

公开(公告)日：2006-12-20

申请号：EP99660147.2

申请日：1999-09-14

Applicant: ATI Technologies Inc. ,  ATI International S.R.L

Inventor： Rakib, Selim Shlomo ,  Bernstein, Zvi

IPC: H03M13/27 ,  H04L1/00 ,  H04B1/707

CPC classification number: H04L1/0071 ,  H03M13/275 ,  H03M13/276 ,  H03M13/2789 ,  H04L1/0003 ,  H04L1/0043 ,  H04L27/3405

公开(公告)号：EP1063801B1

公开(公告)日：2007-04-25

申请号：EP00660117.3

申请日：2000-06-21

Applicant: ATI Technologies Inc. ,  ATI International S.R.L

Inventor： Grimwood, Michael ,  Lind, Paul Alan ,  Rakib, Selim Shlomo

IPC: H04J3/16 ,  H04J13/04

CPC classification number: H04J3/1694

公开(公告)号：EP1553716A3

公开(公告)日：2006-06-07

申请号：EP05075778.0

申请日：1999-05-06

Applicant: ATI Technologies Inc. ,  ATI International S.R.L

Inventor： Grimwood, Michael ,  Knittel, Jim ,  Richardson, Paul ,  Rakib, Selim Shlomo ,  Lind, Paul Alan ,  Artman, Doug

IPC: H04J11/00 ,  H04J13/02 ,  H04J3/06 ,  H04L7/033 ,  H04J3/16

CPC classification number: H04J13/16 ,  H04J3/0682 ,  H04L7/033

Abstract: A bidirectional digital data communication system which generate phase coherent upstream clock and carrier signals from recovered downstream clock generated from a master clock in a central unit. The preferred species uses any downstream dock rate and generates a phase coherent upstream clock so long as the two clock rates can be related by the ratio M/N where M and N are integers. One embodiment uses an MCNS downstream and an SCDMA upstream and uses MNCN timestamp messages in the downstream to achieve an estimate of RU frame offset prior to establishing frame alignment using a ranging process. The use of timestamp messages to estimate the offset is aided by a low jitter method for inserting timestamp messages by avoiding straddling of MPEG packet headers with the sync message. Clock slip is detected by counting upstream clock cycles over a predetermined downstream clock interval and the RU transmitter is shut down if slip is detected to prevent ISI interference from misaligned codes. An SCDMA transmitter for the minislot environment of 802.14 and MCNS is disclosed along with a receiver for the minislot environment using TDMA or SCDMA demultiplexing.

公开(公告)号：EP1553716A8

公开(公告)日：2005-11-30

申请号：EP05075778.0

申请日：1999-05-06

Applicant: ATI Technologies Inc. ,  ATI International S.R.L

Inventor： Grimwood, Michael ,  Knittel, Jim ,  Richardson, Paul ,  Rakib, Selim Shlomo ,  Lind, Paul Alan ,  Artman, Doug

IPC: H04J13/02 ,  H04J3/06 ,  H04J3/16 ,  H04L7/033

CPC classification number: H04J13/16 ,  H04J3/0682 ,  H04L7/033

Abstract: A bidirectional digital data communication system which generate phase coherent upstream clock and carrier signals from recovered downstream clock generated from a master clock in a central unit. The preferred species uses any downstream dock rate and generates a phase coherent upstream clock so long as the two clock rates can be related by the ratio M/N where M and N are integers. One embodiment uses an MCNS downstream and an SCDMA upstream and uses MNCN timestamp messages in the downstream to achieve an estimate of RU frame offset prior to establishing frame alignment using a ranging process. The use of timestamp messages to estimate the offset is aided by a low jitter method for inserting timestamp messages by avoiding straddling of MPEG packet headers with the sync message. Clock slip is detected by counting upstream clock cycles over a predetermined downstream clock interval and the RU transmitter is shut down if slip is detected to prevent ISI interference from misaligned codes. An SCDMA transmitter for the minislot environment of 802.14 and MCNS is disclosed along with a receiver for the minislot environment using TDMA or SCDMA demultiplexing.

Abstract translation: 一种双向数字数据通信系统，由中央单元中的主时钟产生的恢复的下游时钟产生相位一致的上游时钟和载波信号。 优选物种使用任何下游码头速率并产生相位相干上游时钟，只要两个时钟速率可以通过其中M和N是整数的比率M / N相关。 一个实施例使用MCNS下行流和SCDMA上行流并且在下行中使用MNCN时间戳消息以在使用测距过程建立帧对齐之前实现RU帧偏移的估计。 使用时间戳消息来估计偏移量是通过用于插入时间戳消息的低抖动方法来帮助的，这是通过避免跨越带有同步消息的MPEG分组头来实现的。 通过在预定的下游时钟间隔内对上游时钟周期进行计数来检测时钟滑移，并且如果检测到滑动则RU发送器关闭以防止来自未对齐码的ISI干扰。 用于802.14和MCNS的微时隙环境的SCDMA发射机与用于使用TDMA或SCDMA解复用的最小时隙环境的接收机一起被公开。