Abstract:
A package-on-package system (100) has a first subsystem (191) interconnected with a second subsystem (192) by solder connectors. The first subsystem has an insulating, trace- laminated, sheet- like carrier (101), which is laminated (102) with an insulating trace- laminated frame (110) exposing a central portion (103) of the carrier. A first chip (160) is disposed in the central portion, with a second chip (170) on top; the height of the assembled chips approximates the frame height (111). Bondable contact pads (104) are in the central portion, and solderable terminals (121); pitch center-to-center 0.65 mm or less) on the frame. The second subsystem has a laminated substrate (194) with at least one chip attached, and terminals (195) in locations matching the terminals (121) on the frame of the first subsystem. The terminals of both subsystems are interconnected with solder (193) of a higher reflow temperature than additional solder balls (190) for connecting to external parts.
Abstract:
A package-on-package system (100) has a first subsystem (191) interconnected with a second subsystem (192) by solder connectors. The first subsystem has an insulating, trace- laminated, sheet- like carrier (101), which is laminated (102) with an insulating trace- laminated frame (110) exposing a central portion (103) of the carrier. A first chip (160) is disposed in the central portion, with a second chip (170) on top; the height of the assembled chips approximates the frame height (111). Bondable contact pads (104) are in the central portion, and solderable terminals (121); pitch center-to-center 0.65 mm or less) on the frame. The second subsystem has a laminated substrate (194) with at least one chip attached, and terminals (195) in locations matching the terminals (121) on the frame of the first subsystem. The terminals of both subsystems are interconnected with solder (193) of a higher reflow temperature than additional solder balls (190) for connecting to external parts.
Abstract:
A semiconductor system (200) of one or more semiconductor interposers (201 ) with a certain dimension (210), conductive vias (212) extending from the first to the second surface, with terminals and attached non-reflow metal studs (215) at the ends of the vias. A semiconducting interposer surface may include discrete electronic components or an integrated circuit. One or more semiconductor chips (202,203) have a dimension (220,230) narrower than the interposer dimension, and an active surface with terminals and non- reflow metal studs (224,234). One chip is flip-attached to the first interposer surface, and another chip to the second interposer surface, so that the interposer dimension projects over the chip dimension. An insulating substrate (204) has terminals and reflow bodies (242) to connect to the studs of the projecting interposer.
Abstract:
A semiconductor system (300) has one or more packaged active subsystems (310, 330); each subsystem has a substrate with electrical contact pads and one or more semiconductor chips stacked on top of each other, assembled on the substrate. The system further has a packaged passive subsystem (320) including a substrate with electrical contacts and passive electrical components, such as resistors, capacitors, and indictors. The passive subsystem is stacked with the active subsystems and connected to them by solder bodies.
Abstract:
A semiconductor system (300) has one or more packaged active subsystems (310, 330); each subsystem has a substrate with electrical contact pads and one or more semiconductor chips stacked on top of each other, assembled on the substrate. The system further has a packaged passive subsystem (320) including a substrate with electrical contacts and passive electrical components, such as resistors, capacitors, and indictors. The passive subsystem is stacked with the active subsystems and connected to them by solder bodies.