公开(公告)号：WO2004074996A2

公开(公告)日：2004-09-02

申请号：PCT/US2004/004098

申请日：2004-02-12

Applicant: CHAPPARAL NETWORK STORAGE, INC. ,  MAINE, Gene

Inventor： MAINE, Gene

IPC: G06F

CPC classification number: G06F11/2087 ,  G06F3/0601 ,  G06F2003/0692 ,  H04L67/1097

Abstract: A bus bridge apparatus for performing broadcasted writes to redundant memory subsystems in a network storage controller is disclosed. The bus bridge includes a PCI-X target that receives a write command on a first PCI-X bus on one side of the bridge. The target is coupled to two PCI-X masters coupled to primary and secondary memory subsystems by respective PCI-X buses on the other side of the bridge. A first FIFO buffers the write command data between the target and the first master, and a second FIFO buffers a copy of the data between the target and the second master. The first and second masters concurrently retransmit the write command on their respective PCI-X buses to the primary and secondary memory subsystems. However, the second master only retransmits if broadcasting is enabled and the write command address is in a broadcast address range known by the bus bridge.

Abstract translation: 公开了一种用于对网络存储控制器中的冗余存储器子系统进行广播写入的总线桥接装置。 总线桥包括PCI-X目标，它在桥的一侧的第一个PCI-X总线上接收写命令。 目标通过在桥的另一侧上的相应的PCI-X总线耦合到两个PCI-X主站，其耦合到主存储器子系统和辅助存储器子系统。 第一FIFO缓冲目标和第一主机之间的写命令数据，第二FIFO缓冲目标和第二主机之间的数据副本。 第一和第二主器件在其各自的PCI-X总线上同时将写入命令重新发送到主存储器子系统和辅助存储器子系统。 然而，如果广播被使能并且写命令地址是由总线桥已知的广播地址范围，则第二主机仅重传。

公开(公告)号：WO2004074996A3

公开(公告)日：2004-12-29

申请号：PCT/US2004004098

申请日：2004-02-12

Applicant: CHAPPARAL NETWORK STORAGE INC ,  MAINE GENE

Inventor： MAINE GENE

IPC: G06F20060101 ,  G06F3/06 ,  G06F11/20 ,  G06F13/36 ,  G06F15/16

CPC classification number: G06F11/2087 ,  G06F3/0601 ,  G06F2003/0692 ,  H04L67/1097

Abstract: A bus bridge apparatus for performing broadcasted writes to redundant memory subsystems in a network storage controller is disclosed. The bus bridge includes a PCI-X target that receives a write command on a first PCI-X bus on one side of the bridge. The target is coupled to two PCI-X masters coupled to primary and secondary memory subsystems by respective PCI-X buses on the other side of the bridge. A first FIFO buffers the write command data between the target and the first master, and a second FIFO buffers a copy of the data between the target and the second master. The first and second masters concurrently retransmit the write command on their respective PCI-X buses to the primary and secondary memory subsystems. However, the second master only retransmits if broadcasting is enabled and the write command address is in a broadcast address range known by the bus bridge.