公开(公告)号：AU2003269997A1

公开(公告)日：2005-04-14

申请号：AU2003269997

申请日：2003-08-26

Applicant: COOK PETER W ,  EMMA PHILIP G ,  JACOBSON HANS M ,  KUDVA PRABHAKAR N ,  SCHUSTER STANLEY E ,  RIVERS JUDE A ,  ZYUBAN VICTOR V ,  IBM ,  BOSE PRADIP ,  CITRON DANIEL M

Inventor： COOK PETER W ,  EMMA PHILIP G ,  JACOBSON HANS M ,  KUDVA PRABHAKAR N ,  SCHUSTER STANLEY E ,  RIVERS JUDE A ,  ZYUBAN VICTOR V ,  BOSE PRADIP ,  CITRON DANIEL M

IPC: G06F1/04 ,  G06F1/32 ,  G06F9/38

Abstract: A synchronous integrated circuit such as a scalar processor or superscalar processor. Circuit components or units are clocked by and synchronized to a common system clock. At least two of the clocked units include multiple register stages, e.g., pipeline stages. A local clock generator in each clocked unit combines the common system clock and stall status from one or more other units to adjust register clock frequency up or down.

公开(公告)号：WO2005031565A1

公开(公告)日：2005-04-07

申请号：PCT/US2003/026531

申请日：2003-08-26

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  BOSE, Pradip ,  CITRON, Daniel, M. ,  COOK, Peter, W. ,  EMMA, Philip, G. ,  JACOBSON, Hans, M. ,  KUDVA, Prabhakar, N. ,  SCHUSTER, Stanley, E. ,  RIVERS, Jude, A. ,  ZYUBAN, Victor, V.

Inventor： BOSE, Pradip ,  CITRON, Daniel, M. ,  COOK, Peter, W. ,  EMMA, Philip, G. ,  JACOBSON, Hans, M. ,  KUDVA, Prabhakar, N. ,  SCHUSTER, Stanley, E. ,  RIVERS, Jude, A. ,  ZYUBAN, Victor, V.

IPC: G06F9/38

CPC classification number: G06F9/3869 ,  G06F1/04 ,  G06F1/3203 ,  G06F1/3237 ,  G06F1/324 ,  G06F1/3243 ,  G06F1/3287 ,  G06F9/30083 ,  G06F9/3802 ,  G06F9/3836 ,  G06F9/384 ,  G06F9/3867 ,  Y02D10/126 ,  Y02D10/128 ,  Y02D10/152 ,  Y02D10/171

Abstract: A synchronous integrated circuit such as a scalar processor or superscalar processor. Circuit components or units are clocked by and synchronized to a common system clock. At least two of the clocked units include multiple register stages, e.g., pipeline stages. A local clock generator in each clocked unit combines the common system clock and stall status from one or more other units to adjust register clock frequency up or down.

Abstract translation: 同步集成电路，如标量处理器或超标量处理器。 电路组件或单元由公共系统时钟计时并同步。 至少两个时钟单元包括多个寄存器级，例如流水线级。 每个时钟单元中的本地时钟发生器将来自一个或多个其他单元的公共系统时钟和失速状态相结合，以调整寄存器时钟频率向上或向下。