IMPROVED SIDEWALL IMAGE TRANSFER PROCESS
    1.
    发明申请
    IMPROVED SIDEWALL IMAGE TRANSFER PROCESS 审中-公开
    改进的平台图像传输过程

    公开(公告)号:WO2012128843A3

    公开(公告)日:2013-03-14

    申请号:PCT/US2012023065

    申请日:2012-01-30

    CPC classification number: H01L21/0337 H01L21/3086 H01L21/31144 H01L21/32139

    Abstract: An improved method of performing sidewall spacer image transfer is presented. The method includes forming a set of sidewall spacers (109a) next to a plurality of mandrels (106a), the set of sidewall spacers being directly on top of a hard-mask layer (105); transferring image of at least a portion of the set of sidewall spacers to the hard- mask layer to form a device pattern (105a); and transferring the device pattern from the hard- mask layer to a substrate (101) underneath the hard-mask layer.

    Abstract translation: 提出了一种执行侧壁间隔图像转移的改进方法。 该方法包括在多个心轴(106a)旁边形成一组侧壁间隔物(109a),该组侧壁间隔物直接位于硬掩模层(105)的顶部上。 将所述一组侧壁间隔物的至少一部分图像转印到所述硬掩模层以形成器件图案(105a); 以及将所述装置图案从所述硬掩模层转移到所述硬掩模层下方的基板(101)。

    IMPROVED SIDEWALL IMAGE TRANSFER PROCESS
    2.
    发明申请
    IMPROVED SIDEWALL IMAGE TRANSFER PROCESS 审中-公开
    改进的平台图像传输过程

    公开(公告)号:WO2012128843A2

    公开(公告)日:2012-09-27

    申请号:PCT/US2012/023065

    申请日:2012-01-30

    CPC classification number: H01L21/0337 H01L21/3086 H01L21/31144 H01L21/32139

    Abstract: An improved method of performing sidewall spacer image transfer is presented. The method includes forming a set of sidewall spacers (109a) next to a plurality of mandrels (106a), the set of sidewall spacers being directly on top of a hard-mask layer (105); transferring image of at least a portion of the set of sidewall spacers to the hard- mask layer to form a device pattern (105a); and transferring the device pattern from the hard- mask layer to a substrate (101) underneath the hard-mask layer.

    Abstract translation: 提出了一种执行侧壁间隔图像转移的改进方法。 该方法包括在多个心轴(106a)旁边形成一组侧壁间隔物(109a),该组侧壁间隔物直接位于硬掩模层(105)的顶部上。 将所述一组侧壁间隔物的至少一部分图像转印到所述硬掩模层以形成器件图案(105a); 以及将所述装置图案从所述硬掩模层转移到所述硬掩模层下方的基板(101)。

    GATE PATTERNING SCHEME WITH SELF ALIGNED INDEPENDENT GATE ETCH
    3.
    发明申请
    GATE PATTERNING SCHEME WITH SELF ALIGNED INDEPENDENT GATE ETCH 审中-公开
    具有自对准独立门控阀的门控方案

    公开(公告)号:WO2009099987A1

    公开(公告)日:2009-08-13

    申请号:PCT/US2009/032800

    申请日:2009-02-02

    Abstract: A method for self-aligned gate patterning is disclosed. Two masks are used to process adjacent semiconductor components, such as an nFET and pFET that are separated by a shallow trench isolation region. The mask materials are chosen to facilitate selective etching. The second mask is applied while the first mask is still present, thereby causing the second mask to self align to the first mask. This avoids the undesirable formation of a stringer over the shallow trench isolation region, thereby improving the yield of a semiconductor manufacturing operation.

    Abstract translation: 公开了一种用于自对准栅极图案化的方法。 使用两个掩模来处理相邻的半导体部件,例如由浅沟槽隔离区分隔的nFET和pFET。 选择掩模材料以便于选择性蚀刻。 当第一掩模仍然存在时,施加第二掩模,从而使第二掩模与第一掩模自对准。 这避免了在浅沟槽隔离区域上不期望地形成纵梁,从而提高半导体制造操作的产量。

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