公开(公告)号：KR20200136975A

公开(公告)日：2020-12-08

申请号：KR20207030950

申请日：2019-03-27

Applicant: CSMC TECHNOLOGIES FAB2 CO LTD

Inventor： FANG DONG ,  BIAN ZHENG

IPC: H01L29/66 ,  H01L29/423

Abstract: 본발명은트렌치분리게이트디바이스의제조방법에관한것으로, 상기방법은반도체기판을에칭하여트렌치를형성하는단계; 트렌치내에산화물을증착하여플로팅게이트산화층을형성함으로써, 플로팅게이트산화층이트렌치측벽을따라위에서아래로점차두꺼워지고, 트렌치측벽하부에있는플로팅게이트산화층의두께가트렌치밑부분에있는플로팅게이트산화층의두께와동일하게하는단계; 트렌치내에다결정규소를증착하여플로팅게이트다결정층을형성하는단계; 플로팅게이트다결정층의상면에절연매체를생장시켜격리층을형성하는단계; 트렌치내의격리층상에컨트롤게이트를형성하는단계를포함한다.

公开(公告)号：WO2012071988A1

公开(公告)日：2012-06-07

申请号：PCT/CN2011/082406

申请日：2011-11-18

Applicant: CSMC TECHNOLOGIES FAB1 CO., LTD ,  CSMC TECHNOLOGIES FAB2 CO., LTD. ,  WANG, Le

Inventor： WANG, Le

IPC: H01L29/78 ,  H01L29/10 ,  H01L29/423 ,  H01L21/336

CPC classification number: H01L29/78 ,  H01L29/1033 ,  H01L29/66477 ,  H01L29/66651

Abstract: A Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET) is disclosed. The MOSFET includes a substrate, a well region formed in the substrate, a shallow channel layer, a channel, a gate oxide layer, a gate region, a source region, and a drain region. The shallow channel layer is formed on a portion of the well region and includes a first shallow channel region and a second shallow channel region. The channel is arranged between the first shallow channel region and the second shallow channel region and connects the first shallow channel region and the second shallow channel region. Further, the gate oxide layer is formed on a portion of the well region between the first shallow channel region and the second shallow channel region and includes a first gate oxide region and a second gate oxide region arranged on different sides of the channel. The gate region is formed on the channel and the gate oxide layer; the source region is formed in the first shallow channel region and vertically extends into the well region under the first shallow channel region; and the drain region is formed in the second shallow channel region and vertically extends into the well region under the second shallow channel region.

Abstract translation: 公开了一种金属氧化物半导体场效应晶体管（MOSFET）。 MOSFET包括衬底，形成在衬底中的阱区，浅沟道层，沟道，栅极氧化物层，栅极区，源极区和漏极区。 浅沟道层形成在阱区的一部分上，并且包括第一浅沟道区和第二浅沟道区。 通道布置在第一浅沟道区域和第二浅沟道区域之间，并且连接第一浅沟道区域和第二浅沟道区域。 此外，栅极氧化层形成在第一浅沟道区域和第二浅沟道区域之间的阱区域的一部分上，并且包括布置在沟道的不同侧上的第​​一栅极氧化物区域和第二栅极氧化物区域。 栅极区形成在沟道和栅极氧化物层上; 源极区域形成在第一浅沟道区域中并垂直延伸到第一浅沟道区域下方的阱区域中; 并且所述漏极区域形成在所述第二浅沟道区域中并且垂直延伸到所述第二浅沟道区域下方的阱区域中。

公开(公告)号：WO2012028110A1

公开(公告)日：2012-03-08

申请号：PCT/CN2011/079261

申请日：2011-09-01

Applicant: CSMC TECHNOLOGIES FAB1 CO.,LTD. ,  CSMC TECHNOLOGIES FAB2 CO.,LTD. ,  SONG, Hua ,  WU, Hsiao-Chia ,  LO, Tse-Huang

Inventor： SONG, Hua ,  WU, Hsiao-Chia ,  LO, Tse-Huang

IPC: H01L21/316 ,  H01L29/70

CPC classification number: H01L21/265 ,  H01L21/26513 ,  H01L21/74 ,  H01L29/02 ,  H01L29/0821

Abstract: The present disclosure provides a semiconductor device and a method for fabricating a semiconductor buried layer. The method includes: preparing a substrate which includes a first oxide layer; forming a first buried layer region in the surface of the substrate by using a photoresist layer with a first buried layer region pattern as a mask, in which a doping state of the first buried layer region is different from a doping state of other region of the substrate; forming a second oxide layer on the surface of the substrate and the first buried layer region; and forming a second buried layer region in the surface of the substrate through self alignment process by using the second oxide layer as a mask. The method disclosed by the present disclosure reduces the complexity of the buried layer procedures and the cost thereof, as well as the probability of crystal defects.

Abstract translation: 本公开提供了半导体器件和制造半导体掩埋层的方法。 该方法包括：制备包括第一氧化物层的衬底; 通过使用具有第一掩埋层区域图案的光致抗蚀剂层作为掩模，在所述基板的表面中形成第一掩埋层区域，其中所述第一掩埋层区域的掺杂状态与所述第一掩埋层区域的其他区域的掺杂状态不同 基质; 在所述基板的表面和所述第一掩埋层区域上形成第二氧化物层; 以及通过使用第二氧化物层作为掩模通过自对准工艺在衬底的表面中形成第二掩埋层区域。 本发明公开的方法降低了掩埋层工艺的复杂性及其成本，以及晶体缺陷的可能性。

公开(公告)号：WO2011066800A1

公开(公告)日：2011-06-09

申请号：PCT/CN2010/079392

申请日：2010-12-02

Applicant: CSMC TECHNOLOGIES FAB1 CO.,LTD. ,  CSMC TECHNOLOGIES FAB2 CO.,LTD. ,  WANG, Le ,  GUI, Linchun ,  ZHU, Kongwei ,  ZHAO, Zhiyong

Inventor： WANG, Le ,  GUI, Linchun ,  ZHU, Kongwei ,  ZHAO, Zhiyong

IPC: H01L21/331

CPC classification number: H01L29/66272

Abstract: A method for manufacturing a bipolar transistor includes forming a first epitaxial layer (202) on a semiconductor substrate (200), forming a second epitaxial layer (204) on the first epitaxial layer, forming an oxide layer (206) on the second epitaxial layer, etching the oxide layer to form an opening (208) in which the second epitaxial layer is exposed, and forming a third epitaxial layer (210) in the opening. The first and third epitaxial layers have a first-type conductivity, and the second epitaxial layer has a second-type conductivity.

Abstract translation: 一种用于制造双极晶体管的方法，包括在半导体衬底上形成第一外延层（202），在第一外延层上形成第二外延层（204），在第二外延层上形成氧化物层（206） 蚀刻所述氧化物层以形成所述第二外延层暴露的开口（208），以及在所述开口中形成第三外延层（210）。 第一和第三外延层具有第一类型的导电性，第二外延层具有第二类型的导电性。

公开(公告)号：WO2011035727A1

公开(公告)日：2011-03-31

申请号：PCT/CN2010/077318

申请日：2010-09-26

Applicant: CSMC TECHNOLOGIES FAB1 CO.,LTD. ,  CSMC TECHNOLOGIES FAB2 CO.,LTD. ,  WANG, Le

Inventor： WANG, Le

IPC: H01L21/336 ,  H01L29/76

CPC classification number: H01L29/7813 ,  H01L29/42372 ,  H01L29/456 ,  H01L29/4933 ,  H01L29/665 ,  H01L29/66719 ,  H01L29/66734

Abstract: A method for fabricating trench DMOS transistor includes: forming an oxide layer(104) and a barrier layer(106) with photolithography layout sequentially on a semiconductor substrate(100); etching the oxide layer(104) and the semiconductor substrate(100) with the barrier layer(106) as a mask to form a trench(110); forming a gate oxide layer(112) on the inner wall of the trench(110); forming a polysilicon layer on the barrier layer(106), filling up the trench(110); etching back the polysilicon layer with the barrier layer mask to remove the polysilicon layer on the barrier layer(106) to form a trench gate(114); removing the barrier layer(106) and the oxide layer(104); implanting ions into the semiconductor substrate(100) on both sides of the trench gate(114) to form a diffusion layer(115); coating a photoresist layer(116) on the diffusion layer(115) and defining a source/drain layout thereon; implanting ions(117) into the diffusion layer(115) based on the source/drain layout with the photoresist layer(116) mask to form the source/drain(118); forming sidewalls(120) on both the sides of the trench gate(114) after removing the photoresist layer(116); and forming a metal silicide layer(122) on the diffusion layer(115) and the trench gate(114). Effective result is achieved with lower cost and improved efficiency of fabrication.

Abstract translation: 制造沟槽DMOS晶体管的方法包括：在半导体衬底（100）上顺序地形成具有光刻布局的氧化物层（104）和阻挡层（106）; 用所述阻挡层（106）作为掩模蚀刻所述氧化物层（104）和所述半导体衬底（100）以形成沟槽（110）; 在所述沟槽（110）的内壁上形成栅氧化层（112）; 在所述阻挡层（106）上形成多晶硅层，填充所述沟槽（110）; 用阻挡层掩模蚀刻多晶硅层以去除阻挡层（106）上的多晶硅层以形成沟槽栅极（114）; 去除所述阻挡层（106）和所述氧化物层（104）; 将离子注入到沟槽栅极（114）的两侧上的半导体衬底（100）中以形成扩散层（115）; 在所述扩散层（115）上涂覆光致抗蚀剂层（116）并在其上限定源极/漏极布局; 基于具有光致抗蚀剂层（116）的源极/漏极布局将离子（117）注入到扩散层（115）中以形成源极/漏极（118）; 在除去光致抗蚀剂层（116）之后在沟槽栅极（114）的两侧上形成侧壁（120）; 以及在所述扩散层（115）和所述沟槽栅极（114）上形成金属硅化物层（122）。 以较低的成本和提高的制造效率实现有效的结果。

公开(公告)号：WO2012083787A1

公开(公告)日：2012-06-28

申请号：PCT/CN2011/083231

申请日：2011-11-30

Applicant: CSMC TECHNOLOGIES FAB1 CO., LTD ,  CSMC TECHNOLOGIES FAB2 CO., LTD. ,  JIN, Yan

Inventor： JIN, Yan

IPC: H01L21/336 ,  H01L21/8234 ,  H01L29/78

CPC classification number: H01L29/66477 ,  H01L29/42368 ,  H01L29/78 ,  H01L29/7836

Abstract: A metal-oxide-semiconductor (MOS) device is disclosed. The MOS device (20) includes a substrate, a well region (200) formed in the substrate, and a gate (201) located on the substrate. The MOS device (20) also includes a first lightly-doped region (207) arranged in the well region (200) at a first side of the gate (201) and overlapping with the gate (201), and a second lightly-doped region (208) arranged in the well region (200) at a second side of the gate (201) and overlapping with the gate (201). Further, the MOS device (20) includes a first heavily-doped region (205) formed in the first lightly-doped region (207), and a second heavily-doped region (206) formed in the second lightly-doped region (208). The MOS device (20) also includes a first high-low-voltage gate oxide boundary (203) arranged between the first heavily-doped region (205) and the gate (201), and a second high-low-voltage gate oxide boundary (204) arranged between the second heavily-doped region (206) and the gate (201). The gate (201) covers the first high-low-voltage gate oxide boundary (203) and the second high-low-voltage gate oxide boundary (204) at the first side and the second side of the gate (201), respectively. A method is also disclosed.

Abstract translation: 公开了一种金属氧化物半导体（MOS）器件。 MOS器件（20）包括衬底，形成在衬底中的阱区（200）和位于衬底上的栅极（201）。 MOS器件（20）还包括在栅极（201）的第一侧处布置在阱区（200）中并与栅极（201）重叠的第一轻掺杂区域（207），并且第二轻掺杂区域 在门（201）的第二侧上布置在阱区（200）中并与栅极（201）重叠的区域（208）。 此外，MOS器件（20）包括形成在第一轻掺杂区域（207）中的第一重掺杂区域（205）和形成在第二轻掺杂区域（208）中的第二重掺杂区域（206） ）。 MOS器件（20）还包括布置在第一重掺杂区域（205）和栅极（201）之间的第一高低电压栅氧化物边界（203）和第二高低电压栅极氧化物边界 （204），布置在第二重掺杂区域（206）和栅极（201）之间。 栅极（201）分别在栅极（201）的第一侧和第二侧覆盖第一高低压栅极氧化物边界（203）和第二高低压栅极氧化物边界（204）。 还公开了一种方法。

公开(公告)号：WO2012083783A1

公开(公告)日：2012-06-28

申请号：PCT/CN2011/083106

申请日：2011-11-29

Applicant: CSMC TECHNOLOGIES FAB1 CO., LTD ,  CSMC TECHNOLOGIES FAB2 CO., LTD. ,  CAO, Jian ,  ZHAO, Guangyan ,  GAO, Dongyue

Inventor： CAO, Jian ,  ZHAO, Guangyan ,  GAO, Dongyue

IPC: H01L29/78 ,  H01L29/768 ,  H01L21/336

CPC classification number: H01L29/7811 ,  H01L29/41741 ,  H01L29/42372 ,  H01L29/4238

Abstract: A double-diffusion metal-oxide semiconductor (DMOS) device (100) is disclosed. The DMOS device (100) includes a substrate, a source region on the substrate, a gate region on the substrate, and a drain region on the substrate. The DMOS device (100) also includes a source metal layer (101) positioned on the source region and a gate metal layer (102) positioned on the gate region. The source metal layer (101) has a first pattern, the gate metal layer (102) has a second pattern, and the first pattern is different from the second pattern such that the source metal layer (101) can be distinguished from the gate metal layer (102) by packaging equipment based on the different first pattern and second pattern.

Abstract translation: 公开了一种双扩散金属氧化物半导体（DMOS）器件（100）。 DMOS器件（100）包括衬底，衬底上的源极区域，衬底上的栅极区域和衬底上的漏极区域。 DMOS器件（100）还包括位于源极区上的源极金属层（101）和位于栅极区上的栅极金属层（102）。 源极金属层（101）具有第一图案，栅极金属层（102）具有第二图案，并且第一图案与第二图案不同，使得源极金属层（101）可以与栅极金属 通过基于不同的第一图案和第二图案的包装设备来形成层（102）。

公开(公告)号：WO2012079458A1

公开(公告)日：2012-06-21

申请号：PCT/CN2011/083144

申请日：2011-11-29

Applicant: CSMC TECHNOLOGIES FAB1 CO., LTD ,  CSMC TECHNOLOGIES FAB2 CO., LTD. ,  HAN, Guangtao ,  SUN, Guipeng ,  LIN, Feng ,  MA, Chunxia ,  HUANG, Feng

Inventor： HAN, Guangtao ,  SUN, Guipeng ,  LIN, Feng ,  MA, Chunxia ,  HUANG, Feng

IPC: H01L21/336 ,  H01L21/762 ,  H01L29/78 ,  H01L29/06

CPC classification number: H01L21/76224 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/66659 ,  H01L29/7835

Abstract: A method of fabricating a LDMOS device includesproviding a substrate having a body layer, an epitaxial layer overlying the body layer, and a deep well region disposed in a middle portion of the epitaxial layer, forming an isolation dielectric layer on the deep well region and forming a hard mask layer on the isolation dielectric layer, forming a shallow trench in the deep well region by a mask having a drift region pattern, and forming a shallow trench dielectric layer in the shallow trench. The method further includes forming a deep trench at an edge of the deep well region, filling the deep trench with a dielectric material, and planarizing the filled deep trench and the shallow trench dielectric layer. The method also includes forming a groove above the drift region, and filling a dielectric layer in the groove.

Abstract translation: 一种制造LDMOS器件的方法包括提供具有体层的衬底，覆盖在体层上的外延层，以及设置在外延层的中间部分中的深阱区，在深阱区上形成隔离电介质层并形成 在隔离电介质层上的硬掩模层，通过具有漂移区域图案的掩模在深阱区域中形成浅沟槽，并在浅沟槽中形成浅沟槽电介质层。 该方法还包括在深阱区域的边缘处形成深沟槽，用介电材料填充深沟槽，以及平坦化填充的深沟槽和浅沟槽电介质层。 该方法还包括在漂移区上方形成凹槽，并且在沟槽中填充电介质层。

公开(公告)号：WO2012079454A1

公开(公告)日：2012-06-21

申请号：PCT/CN2011/083101

申请日：2011-11-29

Applicant: CSMC TECHNOLOGIES FAB1 CO., LTD. ,  CSMC TECHNOLOGIES FAB2 CO.,LTD. ,  CHENG, Liang

Inventor： CHENG, Liang

IPC: G05F1/565 ,  G05F3/30

CPC classification number: G05F3/02 ,  G05F3/30

Abstract: A reference power supply circuit includes an adjustable resistance network (12) and a bandgap reference power supply circuit (13). The adjustable resistance network (12) includes a first resistor end (PI) and a second resistor end (P2), and the resistance between the first resistor end (PI) and the second resistor end (P2) varies with a process deviation. The bandgap reference power supply circuit (13) connects the first resistor end (PI) with the second resistor end (P2). The bandgap reference power supply circuit (13) generates a positive proportional to absolute temperature current flowing through the first resistor end (PI) and the second resistor (P2), and outputs a reference voltage related to the positive proportional to absolute temperature current. The reference power supply circuit has the advantages of high precision and good temperature drift characteristic.

Abstract translation: 参考电源电路包括可调电阻网络（12）和带隙参考电源电路（13）。 可调电阻网络（12）包括第一电阻端（PI）和第二电阻端（P2），第一电阻端（PI）和第二电阻端（P2）之间的电阻随过程偏差而变化。 带隙参考电源电路（13）将第一电阻器端（PI）与第二电阻端（P2）连接。 带隙参考电源电路（13）产生与流过第一电阻端（PI）和第二电阻器（P2）的绝对温度电流正比，并输出与绝对温度电流正比的参考电压。 参考电源电路具有精度高，温漂特性好的优点。

公开(公告)号：WO2012034372A8

公开(公告)日：2012-03-22

申请号：PCT/CN2011/070950

申请日：2011-02-12

Applicant: CSMC TECHNOLOGIES FAB1 CO., LTD. ,  CSMC TECHNOLOGIES FAB2 CO., LTD. ,  WANG, Genyi ,  WO, Tzong Shiann

Inventor： WANG, Genyi ,  WO, Tzong Shiann

IPC: H01L29/78

Abstract: A trench vertical double diffused metal oxide semiconductor transistor includes, in part, a semiconductor substrate, an epitaxial layer formed above the substrate, a well region formed in the epitaxial layer, a multitude of trenches formed in the well region with each trench having formed therein a gate oxide layer and a polysilicon gate, a multitude of contact holes formed in the well region wherein each contact hole is positioned between a pair of adjacent trenches and has a metal disposed therein, a multitude of body contact regions positioned below the contact holes, and a multitude of source regions formed in the well region. Each source region is positioned between a trench and a contact hole. The substrate, the epitaxial layer, and the source regions are of the first conductivity type. The well region and the body contact regions are of the second conductivity type opposite the first conductivity type.