公开(公告)号：US20190049081A1

公开(公告)日：2019-02-14

申请号：US16001920

申请日：2018-06-06

Applicant: Chia-Lin CHEN

Inventor： Chia-Lin CHEN

IPC: F21S8/04 ,  F21S8/00

Abstract: A lamp power assembling structure and method, the lamp power assembling structure is installed indoors and is connected an indoor power source, and includes a lamp power seat and a lamp fixing seat. The lamp power seat has a first power connector for connecting to the indoor power source and two sliding trenches. Each sliding trench has an arced channel and an enlarged hole formed at an end of the arced channel. The lamp fixing seat has a second power connector corresponding to the first power connector and two fasteners separately corresponding to the two enlarged holes. The two fasteners are separately inserted into the two enlarged holes, and the lamp fixing seat is rotated about the first and second power connectors so as to make the two fasteners separately to be engaged with the arced channels to fix the lamp fixing seat to the lamp power seat.

公开(公告)号：US08115263B2

公开(公告)日：2012-02-14

申请号：US11041178

申请日：2005-01-24

Applicant: Chia-Lin Chen ,  Liang-Gi Yao ,  Shih-Chang Chen

Inventor： Chia-Lin Chen ,  Liang-Gi Yao ,  Shih-Chang Chen

IPC: H01L29/78

CPC classification number: H01L21/02532 ,  H01L21/02595 ,  H01L21/2022 ,  H01L21/28035 ,  H01L21/3003 ,  H01L29/4925 ,  H01L29/78

Abstract: Within a method for forming a silicon layer, there is employed at least one sub-layer formed of a higher crystalline silicon material and at least one sub-layer formed of a lower crystalline silicon material. The lower crystalline silicon material is formed employing a hydrogen treatment of the higher crystalline silicon material. The method is particularly useful for forming polysilicon based gate electrodes with enhanced dimensional control and enhanced performance.

Abstract translation: 在形成硅层的方法中，使用由较高结晶硅材料形成的至少一个子层和由下部结晶硅材料形成的至少一个子层。 使用较高结晶硅材料的氢处理形成下部结晶硅材料。 该方法对于形成具有增强尺寸控制和增强性能的多晶硅基栅电极特别有用。

公开(公告)号：US20110258117A1

公开(公告)日：2011-10-20

申请号：US12760319

申请日：2010-04-14

Applicant: Farhan Ahmad ,  Meeri Siljamaki ,  Min Koo Lee ,  Chia-Lin Chen

Inventor： Farhan Ahmad ,  Meeri Siljamaki ,  Min Koo Lee ,  Chia-Lin Chen

IPC: G06Q20/00 ,  G06F17/30 ,  G06Q30/00

CPC classification number: G06Q20/3224 ,  G06Q20/202 ,  G06Q30/016 ,  G06Q30/0207 ,  G06Q30/06 ,  G06Q40/02

Abstract: A system for, and method of using multiple data flows, both transactional and non-transactional, in real time to modify a transaction is disclosed. Further the use of transaction information in real time as a decision factor to trigger a different, non-transactional response, and the combination of the two approaches is disclosed. In particular, a network comprised of a plurality of software modules and databases is capable of combining current POS/POP transaction data, with a variety of other outside data sources to provide improved information for adjusting responses to transactions in real time. More specifically, the network utilizes payer facing systems to analyze the data in combination with well-known POS/POP transaction data and a variety of internal and external systems to combine information and provide modified transactions, related discounts and offers, and other relevant messaging to the payer. In addition, a specific method for analyzing for fraud within hybrid information transactions is disclosed and several examples to illustrate the invention are included.

Abstract translation: 公开了实时修改事务的用于事务和非事务的多个数据流的系统和方法。 此外，实时地使用交易信息作为触发不同的非交易响应的决定因素，并且公开了这两种方法的组合。 特别地，由多个软件模块和数据库组成的网络能够将当前的POS / POP交易数据与各种其他外部数据源组合，以提供用于实时调整对交易的响应的改进信息。 更具体地说，网络利用面向付费者的系统来与众所周知的POS / POP交易数据和各种内部和外部系统结合来分析数据，以组合信息并提供经修改的交易，相关的折扣和优惠以及其他相关消息传递 付款人。 此外，公开了用于分析混合信息事务中的欺诈的具体方法，并且包括说明本发明的几个示例。

公开(公告)号：US07820457B2

公开(公告)日：2010-10-26

申请号：US11556489

申请日：2006-11-03

Applicant: Chia-Lin Chen ,  Yi-Miaw Lin ,  Ming-Chen Chen

Inventor： Chia-Lin Chen ,  Yi-Miaw Lin ,  Ming-Chen Chen

IPC: G01R31/26

CPC classification number: G01R31/2642 ,  G01R31/2858 ,  G01R31/3008

Abstract: A method includes measuring a gate leakage current of a plurality of transistors. A single stress bias voltage is applied to the plurality of transistors. The stress bias voltage causes a 10% degradation in a drive current of each transistor within a respective stress period t. One or more relationships are determined, between the measured gate leakage current and one or more of the group consisting of gate voltage, gate length, gate temperature, and gate width of the plurality of transistors, respectively. A negative bias temperature instability (NBTI) lifetime τ of the plurality of transistors is estimated, based on the measured gate leakage current and the one or more relationships.

Abstract translation: 一种方法包括测量多个晶体管的栅极漏电流。 单个应力偏置电压被施加到多个晶体管。 应力偏置电压在相应的应力周期t内导致每个晶体管的驱动电流10％的劣化。 在测量的栅极漏电流和分别由多个晶体管的栅极电压，栅极长度，栅极温度和栅极宽度的组中的一个或多个之间确定一个或多个关系。 基于所测量的栅极泄漏电流和一个或多个关系，估计多个晶体管的负偏置温度不稳定性（NBTI）寿命τ。

公开(公告)号：US07696578B2

公开(公告)日：2010-04-13

申请号：US11349804

申请日：2006-02-08

Applicant: Chia-Lin Chen ,  Min-jan Chen ,  Jau-Jey Wang

Inventor： Chia-Lin Chen ,  Min-jan Chen ,  Jau-Jey Wang

IPC: H01L27/092

CPC classification number: H01L21/823807 ,  H01L21/823814 ,  H01L21/823864 ,  H01L29/665 ,  H01L29/66636 ,  H01L29/7843 ,  H01L29/7848

Abstract: A PMOS device less affected by negative bias time instability (NBTI) and a method for forming the same are provided. The PMOS device includes a barrier layer over at least a portion of a gate structure, a gate spacer, and source/drain regions of a PMOS device. A stressed layer is then formed over the barrier layer. The barrier layer is preferably an oxide layer and is preferably not formed for NMOS devices.

Abstract translation: 提供了较少受负偏压时间不稳定性（NBTI）影响的PMOS器件及其形成方法。 PMOS器件在PMOS器件的栅极结构，栅极间隔物和源极/漏极区域的至少一部分上包括阻挡层。 然后在阻挡层上形成应力层。 阻挡层优选为氧化物层，优选不为NMOS器件形成。

公开(公告)号：US20080309365A1

公开(公告)日：2008-12-18

申请号：US11763077

申请日：2007-06-14

Applicant: Pei-Chun Liao ,  Chia-Lin Chen

Inventor： Pei-Chun Liao ,  Chia-Lin Chen

IPC: G01R31/26

CPC classification number: G01R31/2858 ,  G01R31/129 ,  G01R31/2623

Abstract: The current invention provides a method of determining the lifetime of a semiconductor device due to time dependent dielectric breakdown (TDDB). This method includes providing a plurality of samples of dielectric layer disposed as a gate dielectric layer of a MOS transistor, approximating a source/drain current density distribution as a first function of voltage applied on the samples, approximating a substrate current density distribution as a second function of voltage applied on the samples, approximating a dielectric layer lifetime distribution as a third function of source/drain current density and substrate current density in the samples, deriving, from the first, second, and the third functions, an empirical model wherein a dielectric layer lifetime is a function of voltage applied thereon, and using the model to determine dielectric layer lifetime at a pre-determined operating gate voltage.

Abstract translation: 本发明提供一种由于时间依赖介电击穿（TDDB）确定半导体器件的寿命的方法。 该方法包括提供设置为MOS晶体管的栅介质层的介质层的多个样本，其近似源/漏电流密度分布作为施加在样本上的电压的第一函数，将基板电流密度分布近似为第二 作为施加在样品上的电压的函数，近似作为源/漏电流密度和样品中的衬底电流密度的第三函数的介电层寿命分布，从第一，第二和第三函数导出经验模型，其中 介电层寿命是施加在其上的电压的函数，并且使用该模型来确定在预定的工作栅极电压下的介电层寿命。

公开(公告)号：US20080128835A1

公开(公告)日：2008-06-05

申请号：US11746366

申请日：2007-05-09

Applicant: Chia-Lin Chen ,  Liang-Gi Yao ,  Shih-Chang Chen

Inventor： Chia-Lin Chen ,  Liang-Gi Yao ,  Shih-Chang Chen

IPC: H01L29/78

CPC classification number: H01L21/28044 ,  C23C16/24 ,  H01L21/0245 ,  H01L21/02532 ,  H01L21/02595 ,  H01L21/02609 ,  H01L21/0262 ,  H01L21/28052 ,  H01L29/4925

Abstract: A semiconductor device having a random grained polysilicon layer and a method for its manufacture are provided. In one example, the device includes a semiconductor substrate and an insulator layer on the substrate. A first polysilicon layer having a random grained structure is positioned above the insulator layer, a semiconductor alloy layer is positioned above the first polysilicon layer, and a second polysilicon layer is positioned above the semiconductor alloy layer.

Abstract translation: 提供了具有随机晶粒多晶硅层的半导体器件及其制造方法。 在一个示例中，该器件在衬底上包括半导体衬底和绝缘体层。 具有随机晶粒结构的第一多晶硅层位于绝缘体层的上方，半导体合金层位于第一多晶硅层的上方，第二多晶硅层位于半导体合金层的上方。

公开(公告)号：US20070240826A1

公开(公告)日：2007-10-18

申请号：US11405618

申请日：2006-04-18

Applicant: Liang-Gi Yao ,  Chia-Lin Chen ,  Ming-Feng Wang ,  Ming-Feng Yoo ,  Kuen-Chyr Lee ,  Shih-Chang Chen

Inventor： Liang-Gi Yao ,  Chia-Lin Chen ,  Ming-Feng Wang ,  Ming-Feng Yoo ,  Kuen-Chyr Lee ,  Shih-Chang Chen

IPC: H01L21/306 ,  C23F1/00

CPC classification number: H01L21/67069

Abstract: A gas supply device, including: a first source of an inert carrier gas, communicated with a first pipeline; a second source of anhydrous reactive gas, communicated with a second pipeline; a third source of enabling chemical gas of an enabling chemical compound, communicated with a third pipeline; a main pipeline, communicated with the first, second, and third pipelines; and a temperature controller, located on the second pipeline.

Abstract translation: 一种气体供应装置，包括：与第一管道连通的惰性载气的第一源; 与第二管道连通的第二无水反应气源; 与第三管道连通的使能化学化合物化学气体的第三个来源; 一条主要管道，与第一条，第二条和第三条管道通信; 和位于第二管道上的温度控制器。

公开(公告)号：US07268575B1

公开(公告)日：2007-09-11

申请号：US11278827

申请日：2006-04-06

Applicant: Chia-Lin Chen ,  Ming-Chen Chen

Inventor： Chia-Lin Chen ,  Ming-Chen Chen

IPC: G01R31/26

CPC classification number: G01R31/2642 ,  G01R31/2858 ,  G01R31/3008

Abstract: A method includes measuring a gate leakage current of at least one transistor. A single stress bias voltage is applied to the at least one transistor at a given temperature for a stress period t. The stress bias voltage causes a 10% degradation in a drive current of the transistor at the given temperature within the stress period t. A negative bias temperature instability (NBTI) lifetime τ of the transistor is estimated based on the measured gate leakage current and a relationship between drive current degradation and time observed during the applying step.

Abstract translation: 一种方法包括测量至少一个晶体管的栅极漏电流。 在给定温度下，对于至少一个晶体管施加单个应力偏置电压以施加应力周期t。 应力偏置电压在应力周期t内的给定温度下导致晶体管的驱动电流降低10％。 基于所测量的栅极泄漏电流和驱动电流劣化与施加步骤期间观察到的时间之间的关系来估计晶体管的负偏置温度不稳定性（NBTI）寿命ττ。

公开(公告)号：US20070181951A1

公开(公告)日：2007-08-09

申请号：US11349804

申请日：2006-02-08

Applicant: Chia-Lin Chen ,  Min-Jan Chen ,  Jau-Jey Wang

Inventor： Chia-Lin Chen ,  Min-Jan Chen ,  Jau-Jey Wang

IPC: H01L29/76 ,  H01L21/8238

CPC classification number: H01L21/823807 ,  H01L21/823814 ,  H01L21/823864 ,  H01L29/665 ,  H01L29/66636 ,  H01L29/7843 ,  H01L29/7848

Abstract: A PMOS device less affected by negative bias time instability (NBTI) and a method for forming the same are provided. The PMOS device includes a barrier layer over at least a portion of a gate structure, a gate spacer, and source/drain regions of a PMOS device. A stressed layer is then formed over the barrier layer. The barrier layer is preferably an oxide layer and is preferably not formed for NMOS devices.

Abstract translation: 提供了较少受负偏压时间不稳定性（NBTI）影响的PMOS器件及其形成方法。 PMOS器件在PMOS器件的栅极结构，栅极间隔物和源极/漏极区域的至少一部分上包括阻挡层。 然后在阻挡层上形成应力层。 阻挡层优选为氧化物层，优选不为NMOS器件形成。