公开(公告)号：WO2013064917A1

公开(公告)日：2013-05-10

申请号：PCT/IB2012/054460

申请日：2012-08-30

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  IBM UNITED KINGDOM LIMITED ,  IBM (CHINA) INVESTMENT COMPANY LIMITED ,  GUPTA, Lokesh, Mohan ,  ELEFTHERIOU, Evangelos, Stavros ,  KOLTSIDAS, Ioannis ,  HU, Xiao-Yu ,  PLETKA, Roman ,  HAAS, Robert ,  BLINICK, Stephen ,  KALOS, Matthew, Joseph ,  NIELSEN, Karl, Allen ,  BENHASE, Michael, Thomas

Inventor： GUPTA, Lokesh, Mohan ,  ELEFTHERIOU, Evangelos, Stavros ,  KOLTSIDAS, Ioannis ,  HU, Xiao-Yu ,  PLETKA, Roman ,  HAAS, Robert ,  BLINICK, Stephen ,  KALOS, Matthew, Joseph ,  NIELSEN, Karl, Allen ,  BENHASE, Michael, Thomas

IPC: G06F12/08

CPC classification number: G06F3/0619 ,  G06F3/0646 ,  G06F3/0688 ,  G06F12/0246 ,  G06F12/0253 ,  G06F12/0811 ,  G06F12/0862 ,  G06F12/0864 ,  G06F12/0871 ,  G06F12/0897 ,  G06F12/122 ,  G06F12/127 ,  G06F12/128 ,  G06F2212/1016 ,  G06F2212/154 ,  G06F2212/222 ,  G06F2212/283 ,  G06F2212/604 ,  G06F2212/702 ,  G06F2212/7201

Abstract: Exemplary method, system, and computer program product embodiments for efficient track destage in secondary storage in a more effective manner, are provided. In one embodiment, by way of example only, for temporal bits employed with sequential bits for controlling the timing for destaging the track in a primary storage, the temporal bits and sequential bits are transferred from the primary storage to the secondary storage. The temporal bits are allowed to age on the secondary storage. Additional system and computer program product embodiments are disclosed and provide related advantages.

Abstract translation: 提供了用于以更有效的方式在二次存储中有效地追踪排水的示例性方法，系统和计算机程序产品实施例。 在一个实施例中，仅作为示例，对于与用于控制主存储器中的跟踪的定时的顺序位一起使用的时间位，时间位和顺序位从主存储器传送到次存储器。 时间位允许在辅助存储器上老化。 公开了附加的系统和计算机程序产品实施例并提供相关的优点。

公开(公告)号：WO1998052330A1

公开(公告)日：1998-11-19

申请号：PCT/IB1997000554

申请日：1997-05-15

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  COKER, Jonathan, Darrel ,  ELEFTHERIOU, Evangelos, Stavros ,  GALBRAITH, Richard, Leo ,  HIRT, Walter

Inventor： INTERNATIONAL BUSINESS MACHINES CORPORATION

IPC: H04L25/03

CPC classification number: G11B20/10175 ,  G11B20/10009

Abstract: In a maximum likelihood sequence detector for symbol sequences which were equalized in a PR4 equalizer, noise prediction means (35) are provided including infinite impulse response (IIR) filtering, which have noise-whitening capabilities and are imbedded into the maximum likelihood detection process. The resulting INPML detector (10) can be implemented in digital or analog circuit technoology. In addition, a DC-notch filter (44a) and a stochastic gradient procedure can be provided for DC offset compensation and for MR head or signal asymmetry compensation.

Abstract translation: 在PR4均衡器中均衡的符号序列的最大似然序列检测器中，提供具有无限脉冲响应（IIR）滤波的噪声预测装置（35），其具有噪声增白能力并被嵌入到最大似然检测过程中。 所得到的INPML检测器（10）可以用数字或模拟电路技术实现。 此外，可以提供DC陷波滤波器（44a）和随机梯度程序用于DC偏移补偿和用于MR头或信号不对称补偿。

公开(公告)号：IL288055D0

公开(公告)日：2022-01-01

申请号：IL28805521

申请日：2021-11-11

Applicant: IBM ,  LE GALLO BOURDEAU MANUEL ,  KHADDAM ALJAMEH RIDUAN ,  KULL LUKAS ,  FRANCESE PIER ANDREA ,  TOIFL THOMAS ,  SEBASTIAN ABU ,  ELEFTHERIOU EVANGELOS STAVROS

Inventor： LE GALLO-BOURDEAU MANUEL ,  KHADDAM-ALJAMEH RIDUAN ,  KULL LUKAS ,  FRANCESE PIER ANDREA ,  TOIFL THOMAS ,  SEBASTIAN ABU ,  ELEFTHERIOU EVANGELOS STAVROS

Abstract: Methods and apparatus are provided for training an artificial neural network having a succession of neuron layers with interposed synaptic layers each having a respective set of N-bit fixed-point weights {w} for weighting signals propagated between its adjacent neuron layers, via an iterative cycle of signal propagation and weight-update calculation operations. Such a method includes, for each synaptic layer, storing a plurality p of the least-significant bits of each N-bit weight w in digital memory, and storing the next n-bit portion of each weight w in an analog multiply-accumulate unit comprising an array of digital memory elements. Each digital memory element comprises n binary memory cells for storing respective bits of the n-bit portion of a weight, where n≥1 and (p+n+m)=N where m≥0 corresponds to a defined number of most-significant zero bits in weights of the synaptic layer.