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    PLL LOCK MANAGEMENT SYSTEM
    1.
    发明申请
    PLL LOCK MANAGEMENT SYSTEM 审中-公开
    PLL锁定管理系统

    公开(公告)号：WO2006110907A2

    公开(公告)日：2006-10-19

    申请号：PCT/US2006014175

    申请日：2006-04-11

    Applicant: QUALCOMM INC ,  FLORESCU OCTAVIAN ,  FAHIM AMR M ,  NARATHONG CHIEWCHARN

    Inventor： FLORESCU OCTAVIAN ,  FAHIM AMR M ,  NARATHONG CHIEWCHARN

    IPC: H03L7/10 ,  H03L7/093

    CPC classification number: H03L7/199 ,  H03L7/0898 ,  H03L7/10

    Abstract: A PLL includes a charge pump, a loop filter, a VCO, and a calibration unit. The calibration unit performs coarse tuning to select one or multiple frequency ranges, performs fine tuning to determine an initial control voltage that puts the VCO near a desired operating frequency, measures the VCO gain at different control voltages, and derives VCO gain compensation values for the different control voltages. The calibration unit also pre-charges the loop filter to the initial control voltage to shorten acquisition time, enables the loop filter to drive the VCO to lock to the desired operating frequency, and performs VCO gain compensation during normal operation. For VCO gain compensation, the calibration unit measures the control voltage, obtains the VCO gain compensation value for the measured control voltage, and adjusts the gain of at least one circuit block (e.g., the charge pump) to account for variation in the VCO gain.

    Abstract translation: PLL包括电荷泵，环路滤波器，VCO和校准单元。 校准单元执行粗调以选择一个或多个频率范围，执行微调以确定将VCO置于所需工作频率附近的初始控制电压，测量不同控制电压下的VCO增益，并导出VCO增益补偿值 不同的控制电压。 校准单元还将环路滤波器预充电到初始控制电压以缩短采集时间，使环路滤波器能够驱动VCO锁定到所需的工作频率，并在正常操作期间执行VCO增益补偿。 对于VCO增益补偿，校准单元测量控制电压，获得测量的控制电压的VCO增益补偿值，并调整至少一个电路块（例如，电荷泵）的增益，以考虑VCO增益的变化 。

    PLL LOCK MANAGEMENT SYSTEM
    2.
    发明申请
    PLL LOCK MANAGEMENT SYSTEM 审中-公开

    公开(公告)号：WO2006110907A3

    公开(公告)日：2006-10-19

    申请号：PCT/US2006/014175

    申请日：2006-04-11

    Applicant: QUALCOMM INCORPORATED ,  FLORESCU, Octavian ,  FAHIM, Amr, M. ,  NARATHONG, Chiewcharn

    Inventor： FLORESCU, Octavian ,  FAHIM, Amr, M. ,  NARATHONG, Chiewcharn

    IPC: H03L7/10 ,  H03L7/093 ,  H03L7/18

    Abstract: A PLL includes a charge pump (320), a loop filter (330) , a VCO (340) , and a calibration unit (360) . The calibration unit (360) performs coarse tuning to select one or multiple frequency ranges, performs fine tuning to determine an initial control voltage that puts the VCO (340) near a desired operating frequency, measures the VCO gain at different control voltages, and derives VCO gain compensation values for the different control voltages. The calibration unit (360) also pre-charges the loop filter (330) to the initial control voltage to shorten acquisition time, enables the loop filter to drive the VCO to lock to the desired operating frequency, and performs VCO gain compensation during normal operation. For VCO gain compensation, the calibration unit measures the control voltage, obtains the VCO gain compensation value for the measured control voltage, and adjusts the gain of at least one circuit block (e.g., the charge pump) to account for variation in the VCO gain.

    LOW-POWER DIRECT DIGITAL SYNTHESIZER WITH ANALOG INTERPOLATION
    3.
    发明申请
    LOW-POWER DIRECT DIGITAL SYNTHESIZER WITH ANALOG INTERPOLATION 审中-公开
    具有模拟插值功能的低功耗直接数字合成器

    公开(公告)号：WO2005038636A1

    公开(公告)日：2005-04-28

    申请号：PCT/US2004/034241

    申请日：2004-10-14

    Applicant: QUALCOMM INCORPORATED ,  FAHIM, Amr M.

    Inventor： FAHIM, Amr M.

    IPC: G06F1/02

    CPC classification number: G06F1/022 ,  G06F1/08 ,  G06F2211/902 ,  H03K5/135 ,  H03K5/1565 ,  H03K2005/00032 ,  H03K2005/00071 ,  H03L7/0814

    Abstract: An MN counter with analog interpolation (an "MNA counter") includes an MN counter, a multiplier, a delay generator, and a current generator. The MN counter receives an input clock signal and M and N values, accumulates M for each input clock cycle using a modulo-N accumulator, and provides an accumulator value and a counter signal with the desired frequency. The multiplier multiplies the accumulator value with an inverse of M and provides an L-bit control signal. The current generator implements a current locked loop that provides a reference current for the delay generator. The delay generator is implemented with a differential design, receives the counter signal and the L-bit control signal, compares a differential signal generated based on the counter and control signals, and provides the output clock signal. The leading edges of the output clock signal have variable delay determined by the L-bit control signal and the reference current.

    Abstract translation: 具有模拟插值的MN计数器（“MNA计数器”）包括MN计数器，乘法器，延迟发生器和电流发生器。 MN计数器接收输入时钟信号和M和N值，使用模N累加器为每个输入时钟周期累加M，并提供具有所需频率的累加器值和计数器信号。 乘法器将累加器值乘以M的倒数，并提供L位控制信号。 电流发生器实现电流锁定环，为延迟发生器提供参考电流。 延迟发生器通过差分设计实现，接收计数器信号和L位控制信号，比较基于计数器和控制信号产生的差分信号，并提供输出时钟信号。 输出时钟信号的前沿具有由L位控制信号和参考电流确定的可变延迟。

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