公开(公告)号：WO2007142167A8

公开(公告)日：2008-06-26

申请号：PCT/JP2007061242

申请日：2007-05-28

Applicant: KOCHI IND PROMOTION CT ,  CASIO COMPUTER CO LTD ,  HIRAO TAKASHI ,  HIRAMATSU TAKAHIRO ,  FURUTA MAMORU ,  FURUTA HIROSHI ,  MATSUDA TOKIYOSHI

Inventor： HIRAO TAKASHI ,  HIRAMATSU TAKAHIRO ,  FURUTA MAMORU ,  FURUTA HIROSHI ,  MATSUDA TOKIYOSHI

IPC: H01L29/786

CPC classification number: H01L29/7869 ,  H01L29/04 ,  H01L29/045 ,  H01L29/78618

Abstract: A semiconductor device includes an oxide semiconductor thin film layer (3) of zinc oxide. The (002) lattice planes of at least a part of the oxide semiconductor thin film layer have a preferred orientation along a direction perpendicular to a substrate (l) of the semiconductor device and a lattice spacing doo2 of at least 2.619A.

Abstract translation: 半导体器件包括氧化锌的氧化物半导体薄膜层（3）。 氧化物半导体薄膜层的至少一部分的（002）晶格面沿着与半导体器件的衬底（1）垂直的方向具有优选取向，并且晶格间距doo2至少为2.619A。

公开(公告)号：WO2007089048A3

公开(公告)日：2007-11-22

申请号：PCT/JP2007052310

申请日：2007-02-02

Applicant: KOCHI IND PROMOTION CT ,  CASIO COMPUTER CO LTD ,  FURUTA MAMORU ,  HIRAO TAKASHI ,  FURUTA HIROSHI ,  MATSUDA TOKIYOSHI ,  HIRAMATSU TAKAHIRO ,  ISHII HIROMITSU ,  HOKARI HITOSHI ,  YOSHIDA MOTOHIKO

Inventor： FURUTA MAMORU ,  HIRAO TAKASHI ,  FURUTA HIROSHI ,  MATSUDA TOKIYOSHI ,  HIRAMATSU TAKAHIRO ,  ISHII HIROMITSU ,  HOKARI HITOSHI ,  YOSHIDA MOTOHIKO

IPC: H01L29/786 ,  H01L29/417

CPC classification number: H01L29/7869 ,  H01L29/41733 ,  H01L29/42384 ,  H01L29/66969 ,  H01L29/78606 ,  H01L29/78618

Abstract: A thin film transistor includes a substrate (1, 11) , and a pair of source/drain electrodes (2, 14) (i.e. , a source electrode and a drain electrode) formed on the substrate and defining a gap therebetween. A pair of low resistance conductive thin films (10, 20) are provided such that each coats at least a part of one of the source/drain electrodes. The low resistance conductive thin films define a gap therebetween. An oxide semiconductor thin film layer (3, 15) is continuously formed on upper surfaces of the pair of low resistance conductive thin films and extends along the gap defined between the low resistance conductive thin films so as to function as a channel. Side surfaces of the oxide semiconductor thin film layer and corresponding side surfaces of the low resistance conductive thin films coincide with each other in a channel width direction of the channel.

Abstract translation: 薄膜晶体管包括基板（1,11），以及形成在基板上并在其之间形成间隙的一对源极/漏极（2,14）（即源电极和漏电极）。 提供一对低电阻导电薄膜（10,20），使得每个涂覆源极/漏极之一的至少一部分。 低电阻导电薄膜在它们之间限定了间隙。 在一对低电阻导电薄膜的上表面上连续地形成氧化物半导体薄膜层（3,15），并沿着限定在低电阻导电薄膜之间的间隙延伸，以作为通道。 氧化物半导体薄膜层的侧表面和低电阻导电薄膜的相应侧表面在沟道的沟道宽度方向上彼此重合。

公开(公告)号：WO2007142167A1

公开(公告)日：2007-12-13

申请号：PCT/JP2007/061242

申请日：2007-05-28

Applicant: KOCHI INDUSTRIAL PROMOTION CENTER ,  CASIO COMPUTER CO., LTD. ,  HIRAO, Taskashi ,  HIRAMATSU, Takahiro ,  FURUTA, Mamoru ,  MATSUDA, Tokiyoshi

Inventor： HIRAO, Taskashi ,  HIRAMATSU, Takahiro ,  FURUTA, Mamoru ,  MATSUDA, Tokiyoshi

IPC: H01L29/786

CPC classification number: H01L29/7869 ,  H01L29/04 ,  H01L29/045 ,  H01L29/78618

Abstract: A semiconductor device includes an oxide semiconductor thin film layer (3) of zinc oxide. The (002) lattice planes of at least a part of the oxide semiconductor thin film layer have a preferred orientation along a direction perpendicular to a substrate (l) of the semiconductor device and a lattice spacing doo2 of at least 2.619A.

Abstract translation: 半导体器件包括氧化锌的氧化物半导体薄膜层（3）。 氧化物半导体薄膜层的至少一部分的（002）晶格面沿着与半导体器件的衬底（1）垂直的方向具有优选取向，并且晶格间距doo2至少为2.619A。

公开(公告)号：WO2007094501A1

公开(公告)日：2007-08-23

申请号：PCT/JP2007/053119

申请日：2007-02-13

Applicant: Kochi Industrial Promotion Center ,  CASIO COMPUTER CO., LTD. ,  HIRAO, Takashi ,  FURUTA, Mamoru ,  FURUTA, Hiroshi ,  MATSUDA, Tokiyoshi ,  HIRAMATSU, Takahiro

Inventor： HIRAO, Takashi ,  FURUTA, Mamoru ,  FURUTA, Hiroshi ,  MATSUDA, Tokiyoshi ,  HIRAMATSU, Takahiro

IPC: H01L21/363

CPC classification number: H01L21/02422 ,  H01L21/02491 ,  H01L21/02494 ,  H01L21/02554 ,  H01L21/02595 ,  H01L21/02609 ,  H01L21/02631 ,  H01L29/04 ,  H01L29/045 ,  H01L29/4908 ,  H01L29/7869 ,  H01L29/78693

Abstract: A semiconductor device includes an oxide semiconductor thin film layer (3) primarily including zinc oxide having at least one orientation other than (002) orientation. The zinc oxide may have a mixed orientation including (002) orientation and (101) orientation. Alternatively, the zinc oxide may have a mixed orientation including (100) orientation and (l0l) orientation.

Abstract translation: 半导体器件包括主要包括具有除（002）取向之外的至少一个取向的氧化锌的氧化物半导体薄膜层（3）。 氧化锌可以具有包括（002）取向和（101）取向的混合取向。 或者，氧化锌可以具有包括（100）取向和（111）取向的混合取向。

公开(公告)号：WO2007089048A2

公开(公告)日：2007-08-09

申请号：PCT/JP2007/052310

申请日：2007-02-02

Applicant: KOCHI INDUSTRIAL PROMOTION CENTER ,  CASIO COMPUTER CO., LTD. ,  FURUTA, Mamoru ,  HIRAO, Takashi ,  FURUTA, Hiroshi ,  MATSUDA, Tokiyoshi ,  HIRAMATSU, Takahiro ,  ISHII, Hiromitsu ,  HOKARI, Hitoshi ,  YOSHIDA, Motohiko

Inventor： FURUTA, Mamoru ,  HIRAO, Takashi ,  FURUTA, Hiroshi ,  MATSUDA, Tokiyoshi ,  HIRAMATSU, Takahiro ,  ISHII, Hiromitsu ,  HOKARI, Hitoshi ,  YOSHIDA, Motohiko

IPC: H01L29/786

CPC classification number: H01L29/7869 ,  H01L29/41733 ,  H01L29/42384 ,  H01L29/66969 ,  H01L29/78606 ,  H01L29/78618

Abstract: A thin film transistor includes a substrate (1, 11), and a pair of source/drain electrodes (2, 14) (i.e., a source electrode and a drain electrode) formed on the substrate and defining a gap therebetween. A pair of low resistance conductive thin films (10, 20) are provided such that each coats at least a part of one of the source/drain electrodes. The low resistance conductive thin films define a gap therebetween. An oxide semiconductor thin film layer (3, 15) is continuously formed on upper surfaces of the pair of low resistance conductive thin films and extends along the gap defined between the low resistance conductive thin films so as to function as a channel. Side surfaces of the oxide semiconductor thin film layer and corresponding side surfaces of the low resistance conductive thin films coincide with each other in a channel width direction of the channel.

Abstract translation: 薄膜晶体管包括基板（1,11），以及形成在基板上并在其之间形成间隙的一对源极/漏极（2,14）（即源电极和漏电极）。 提供一对低电阻导电薄膜（10,20），使得每个涂覆源极/漏极之一的至少一部分。 低电阻导电薄膜在它们之间限定了间隙。 在一对低电阻导电薄膜的上表面上连续地形成氧化物半导体薄膜层（3,15），并沿着限定在低电阻导电薄膜之间的间隙延伸，以作为通道。 氧化物半导体薄膜层的侧表面和低电阻导电薄膜的相应侧表面在沟道的沟道宽度方向上彼此重合。