公开(公告)号：WO2011011757A1

公开(公告)日：2011-01-27

申请号：PCT/US2010/043156

申请日：2010-07-23

Applicant: QUALCOMM Incorporated ,  PLETCHER, Nathan M. ,  HADJICHRISTOS, Aristotele ,  ZHAO, Yu ,  NEJATI, Babak

Inventor： PLETCHER, Nathan M. ,  HADJICHRISTOS, Aristotele ,  ZHAO, Yu ,  NEJATI, Babak

IPC: H04B1/04 ,  H03F1/56

CPC classification number: H04B1/0458 ,  H03F1/56 ,  H03F3/245 ,  H04B1/406

Abstract: Exemplary embodiments are directed to a transmitter with a power amplifier and a switched output matching circuit implementing a plurality of output paths for a plurality of operating modes is described. The power amplifier receives an input RF signal and provides an amplified RF signal. An output matching network performs impedance transformation from low impedance at the power amplifier output to higher impedance at the matching network output. The plurality of output paths are coupled to the output matching network. Each output path provides a different target output impedance for the power amplifier and routes the amplified RF signal from the power amplifier to an antenna when that output path is selected. Each output path may include a matching network coupled in series with a switch. The matching network provides the target output impedance for the power amplifier when the output path is selected. The switch couples or decouples the output path to/from the power amplifier.

Abstract translation: 示例性实施例涉及具有功率放大器和实现用于多个操作模式的多个输出路径的切换输出匹配电路的发射机。 功率放大器接收输入RF信号并提供放大的RF信号。 输出匹配网络执行从功率放大器输出端的低阻抗到匹配网络输出端的较高阻抗的阻抗变换。 多个输出路径耦合到输出匹配网络。 当选择该输出路径时，每个输出路径为功率放大器提供不同的目标输出阻抗，并将放大的RF信号从功率放大器路由到天线。 每个输出路径可以包括与开关串联耦合的匹配网络。 当选择输出路径时，匹配网络为功率放大器提供目标输出阻抗。 开关将输出路径耦合到/从功率放大器解耦。

公开(公告)号：WO2011008562A2

公开(公告)日：2011-01-20

申请号：PCT/US2010040488

申请日：2010-06-29

Applicant: QUALCOMM INC ,  KLEMENS GUY ,  MYERS THOMAS A ,  FREDERICK JR NORMAN L ,  ZHAO YU ,  NEJATI BABAK ,  PLETCHER NATHAN M ,  HADJICHRISTOS ARISTOTELE

Inventor： KLEMENS GUY ,  MYERS THOMAS A ,  FREDERICK JR NORMAN L ,  ZHAO YU ,  NEJATI BABAK ,  PLETCHER NATHAN M ,  HADJICHRISTOS ARISTOTELE

IPC: H01L23/64 ,  H03F3/195

CPC classification number: H03F3/195 ,  H01L23/645 ,  H01L23/66 ,  H01L2223/6655 ,  H01L2223/6661 ,  H01L2224/16225 ,  H01L2924/00014 ,  H01L2924/1305 ,  H01L2924/19015 ,  H01L2924/3011 ,  H01L2924/00 ,  H01L2224/0401

Abstract: A compact integrated power amplifier is described herein. In an exemplary design, an apparatus includes (i) an integrated circuit (IC) die having at least one transistor for a power amplifier and (ii) an IC package having a load inductor for the power amplifier. The IC die is mounted on the IC package with the transistor(s) located over the load inductor. In an exemplary design, the IC die includes a transistor manifold that is placed over the load inductor on the IC package. The transistor(s) are fabricated in the transistor manifold, have a drain connection in the center of the transistor manifold, and have source connections on two sides of the transistor manifold. The IC die and the IC package may include one or more additional power amplifiers. The transistor(s) for each power amplifier may be located over the load inductor for that power amplifier.

Abstract translation: 这里描述了紧凑的集成功率放大器。 在示例性设计中，装置包括（i）具有用于功率放大器的至少一个晶体管的集成电路（IC）管芯，以及（ii）具有用于功率放大器的负载电感器的IC封装。 IC芯片安装在IC封装上，晶体管位于负载感应器上方。 在示例性设计中，IC管芯包括放置在IC封装上的负载电感器上的晶体管歧管。 晶体管制造在晶体管歧管中，在晶体管歧管的中心具有漏极连接，并且在晶体管歧管的两侧具有源极连接。 IC芯片和IC封装可以包括一个或多个附加的功率放大器。 每个功率放大器的晶体管可以位于该功率放大器的负载电感上。

公开(公告)号：WO2010148407A2

公开(公告)日：2010-12-23

申请号：PCT/US2010/039376

申请日：2010-06-21

Applicant: QUALCOMM INCORPORATED ,  SEE, Puay Hoe ,  BALLANTYNE, Gary John ,  SAHOTA, Gurkanwal Singh ,  HADJICHRISTOS, Aristotele ,  CICALINI, Alberto

Inventor： SEE, Puay Hoe ,  BALLANTYNE, Gary John ,  SAHOTA, Gurkanwal Singh ,  HADJICHRISTOS, Aristotele ,  CICALINI, Alberto

IPC: H04B1/04

CPC classification number: H04B1/0458 ,  H03H7/40

Abstract: Exemplary embodiments disclosed are directed to power and impedance measurement circuits that may be used to measure power and/or impedance are described. A measurement circuit may include a sensor and a computation unit. The sensor may sense (i) a first voltage signal across a series circuit coupled to a load to obtain a first sensed signal and (ii) a second voltage signal at a designated end of the series circuit to obtain a second sensed signal. The sensor may mix (i) a first version of the first sensed signal with a first version of the second sensed signal to obtain a first sensor output and (ii) a second version of the first sensed signal with a second version of the second sensed signal to obtain a second sensor output. The computation unit may determine the impedance and/or delivered power at the designated end of the series circuit based on the sensor outputs.

Abstract translation: 所公开的示例性实施例涉及可用于测量功率和/或阻抗的功率和阻抗测量电路。 测量电路可以包括传感器和计算单元。 传感器可以感测（i）跨耦合到负载的串联电路的第一电压信号以获得第一感测信号，以及（ii）串联电路的指定端的第二电压信号以获得第二感测信号。 传感器可以将（i）第一感测信号的第一版本与第二感测信号的第一版本混合以获得第一传感器输出，以及（ii）第一感测信号的第二版本，具有第二感测的第二版本 信号以获得第二传感器输出。 计算单元可以基于传感器输出来确定串联电路的指定端处的阻抗和/或传递功率。

公开(公告)号：WO2002082633A3

公开(公告)日：2002-10-17

申请号：PCT/US2002/007788

申请日：2002-03-11

Applicant: ERICSSON INC. ,  HADJICHRISTOS, Aristotele ,  PEHLKE, David

Inventor： HADJICHRISTOS, Aristotele ,  PEHLKE, David

IPC: H03C1/36

Abstract: An amplifier circuit includes a power amplifier biased for saturated mode operation, and a contrallable current source to provide current to the power amplifer. The controllable current source effects desired amplitude modulation of the output signal from the power amplifier by modulating the supply current it provides responsive to an amplitude information signal.

公开(公告)号：WO2013025953A1

公开(公告)日：2013-02-21

申请号：PCT/US2012/051237

申请日：2012-08-16

Applicant: QUALCOMM INCORPORATED ,  HADJICHRISTOS, Aristotele ,  SAHOTA, Gurkanwal Singh

Inventor： HADJICHRISTOS, Aristotele ,  SAHOTA, Gurkanwal Singh

IPC: H04B1/00 ,  H04B1/40 ,  H03F3/45

CPC classification number: H04B1/0057 ,  H03F1/0277 ,  H03F1/223 ,  H03F1/56 ,  H03F3/211 ,  H03F3/45179 ,  H03F3/68 ,  H03F3/72 ,  H03F2200/222 ,  H03F2200/294 ,  H03F2200/429 ,  H03F2203/7203 ,  H03F2203/7236 ,  H04B1/406

Abstract: Multiple low noise amplifiers (LNAs) with combined outputs are disclosed. In an exemplary design, an apparatus includes a front-end module and an integrated circuit (IC). The front-end module includes a plurality of LNAs having outputs that are combined. The IC includes receive circuits coupled to the plurality of LNAs via a single interconnection. In an exemplary design, each of the plurality of LNAs may be enabled or disabled via a respective control signal for that LNA. The front-end module may also include receive filters coupled to the plurality of LNAs and a switchplexer coupled to the receive filters. The front-end module may further include at least one power amplifier, and the IC may further include transmit circuits coupled to the at least one power amplifier.

Abstract translation: 公开了具有组合输出的多个低噪声放大器（LNA）。 在示例性设计中，装置包括前端模块和集成电路（IC）。 前端模块包括具有组合的输出的多个LNA。 IC包括经由单个互连耦合到多个LNA的接收电路。 在示例性设计中，可以经由用于该LNA的相应控制信号来启用或禁用多个LNA中的每一个。 前端模块还可以包括耦合到多个LNA的接收滤波器和耦合到接收滤波器的交换器。 前端模块还可以包括至少一个功率放大器，并且IC还可以包括耦合到至少一个功率放大器的发射电路。

公开(公告)号：WO2012040063A1

公开(公告)日：2012-03-29

申请号：PCT/US2011/052017

申请日：2011-09-16

Applicant: QUALCOMM MEMS TECHNOLOGIES, INC. ,  BLACK, Justin, Phelps ,  SHENOY, Ravindra, V. ,  GOUSEV, Evgeni, Petrovich ,  HADJICHRISTOS, Aristotele ,  MYERS, Thomas, Andrew ,  KIM, Jonghae ,  VELEZ, Mario, Francisco ,  LAN, Je-Hsiung, Jeffrey ,  LO, Chi, Shun

Inventor： BLACK, Justin, Phelps ,  SHENOY, Ravindra, V. ,  GOUSEV, Evgeni, Petrovich ,  HADJICHRISTOS, Aristotele ,  MYERS, Thomas, Andrew ,  KIM, Jonghae ,  VELEZ, Mario, Francisco ,  LAN, Je-Hsiung, Jeffrey ,  LO, Chi, Shun

IPC: H01L21/56 ,  G02B26/00

CPC classification number: G02B26/001 ,  H01L21/565 ,  H01L23/3128 ,  H01L2224/16225 ,  H01L2924/09701 ,  H01L2924/12044 ,  H01L2924/1461 ,  H01L2924/00

Abstract: This disclosure provides systems, methods and apparatus for combining devices deposited on a first substrate, with integrated circuits formed on a second substrate such as a semiconducting substrate or a glass substrate. The first substrate may be a glass substrate. The first substrate may include conductive vias. A power combiner circuit may be deposited on a first side of the first substrate. The power combiner circuit may include passive devices deposited on at least the first side of the first substrate. The integrated circuit may include a power amplifier circuit disposed on and configured for electrical connection with the power combiner circuit, to form a power amplification system. The conductive vias may include thermal vias configured for conducting heat from the power amplification system and/or interconnect vias configured for electrical connection between the power amplification system and a conductor on a second side of the first substrate.

Abstract translation: 本公开提供了用于组合沉积在第一衬底上的器件与形成在第二衬底（例如半导体衬底或玻璃衬底）上的集成电路的系统，方法和装置。 第一基板可以是玻璃基板。 第一衬底可以包括导电通孔。 功率组合器电路可以沉积在第一衬底的第一侧上。 功率组合器电路可以包括沉积在第一衬底的至少第一侧上的无源器件。 集成电路可以包括设置在功率合成器电路上并被配置为与功率组合器电路电连接的功率放大器电路，以形成功率放大系统。 导电通孔可以包括被配置为用于传导来自功率放大系统的热的热通孔和/或配置用于功率放大系统和第一衬底的第二侧上的导体之间的电连接的互连通孔。

公开(公告)号：WO2011022549A3

公开(公告)日：2011-04-21

申请号：PCT/US2010046021

申请日：2010-08-19

Applicant: QUALCOMM INC ,  ZHAO YU ,  NEJATI BABAK ,  PLETCHER NATHAN M ,  HADJICHRISTOS ARISTOTELE

Inventor： ZHAO YU ,  NEJATI BABAK ,  PLETCHER NATHAN M ,  HADJICHRISTOS ARISTOTELE

IPC: H03H7/38 ,  H03F1/42 ,  H03F3/00 ,  H03F3/193

CPC classification number: H03F1/42 ,  H03F1/223 ,  H03F3/193 ,  H03F2200/318 ,  H03H7/40

Abstract: A tunable inter-stage matching circuit that can improve performance is described. In an exemplary design, an apparatus includes a first active circuit (e.g., a driver amplifier), a second active circuit (e.g., a power amplifier), and a tunable inter-stage matching circuit coupled between the first and second active circuits. The tunable inter-stage matching circuit includes a tunable capacitor that can be varied in discrete steps to adjust impedance matching between the first and second active circuits. In an exemplary design, the tunable capacitor includes (i) a plurality of capacitors coupled in parallel and (ii) a plurality of switches coupled to the plurality of capacitors, one switch for each capacitor. Each switch may be turned on to select an associated capacitor or turned off to unselect the associated capacitor. The tunable capacitor may further include a fixed capacitor coupled in parallel with the plurality of capacitors.

Abstract translation: 描述了可以提高性能的可调谐级间匹配电路。 在示例性设计中，装置包括耦合在第一和第二有源电路之间的第一有源电路（例如，驱动器放大器），第二有源电路（例如，功率放大器）和可调谐级间匹配电路。 可调谐级间匹配电路包括可以在离散步骤中变化的可调谐电容器，以调整第一和第二有源电路之间的阻抗匹配。 在示例性设计中，可调谐电容器包括（i）并联耦合的多个电容器和（ii）耦合到多个电容器的多个开关，用于每个电容器的一个开关。 每个开关可以被接通以选择一个相关联的电容器或关闭以取消选择相关联的电容器。 可调谐电容器还可以包括与多个电容器并联耦合的固定电容器。

公开(公告)号：WO2011017368A1

公开(公告)日：2011-02-10

申请号：PCT/US2010/044306

申请日：2010-08-03

Applicant: QUALCOMM INCORPORATED ,  NEJATI, Babak ,  ZHAO, Yu ,  PLETCHER, Nathan M. ,  HADJICHRISTOS, Aristotele ,  SEE, Puay Hoe

Inventor： NEJATI, Babak ,  ZHAO, Yu ,  PLETCHER, Nathan M. ,  HADJICHRISTOS, Aristotele ,  SEE, Puay Hoe

IPC: H03F1/56 ,  H03F3/72

CPC classification number: H03F1/565 ,  H03F3/211 ,  H03F3/72

Abstract: Exemplary techniques for performing impedance matching are described. In an exemplary embodiment, the apparatus may include an amplifier (e.g., a power amplifier) coupled to first and second matching circuits. The first matching circuit may include multiple stages coupled to a first node and may provide input impedance matching for the amplifier. The second matching circuit may include multiple stages coupled to a second node and may provide output impedance matching for the amplifier. At least one switch may be coupled between the first and second nodes and may bypass or select the amplifier. The first and second nodes may have a common impedance. The apparatus may further include a second amplifier coupled in parallel with the amplifier and further to the matching circuits. The second matching circuit may include a first input stage coupled to the amplifier, a second input stage coupled to the second amplifier, and a second stage coupled to the two input stages via switches.

Abstract translation: 描述了用于执行阻抗匹配的示例性技术。 在示例性实施例中，该装置可以包括耦合到第一和第二匹配电路的放大器（例如功率放大器）。 第一匹配电路可以包括耦合到第一节点的多个级并且可以为放大器提供输入阻抗匹配。 第二匹配电路可以包括耦合到第二节点的多个级并且可以为放大器提供输出阻抗匹配。 至少一个开关可以耦合在第一和第二节点之间，并且可以旁路或选择放大器。 第一和第二节点可以具有公共阻抗。 该装置还可以包括与放大器并联并且进一步耦合到匹配电路的第二放大器。 第二匹配电路可以包括耦合到放大器的第一输入级，耦合到第二放大器的第二输入级，以及经由开关耦合到两个输入级的第二级。

公开(公告)号：WO2010132618A1

公开(公告)日：2010-11-18

申请号：PCT/US2010/034621

申请日：2010-05-12

Applicant: QUALCOMM INCORPORATED ,  HADJICHRISTOS, Aristotele ,  SEE, Puay Hoe ,  NEJATI, Babak ,  KLEMENS, Guy ,  FREDERICK, Norman, L., Jr. ,  SAHOTA, Gurkanwal, Singh ,  CASSIA, Marco ,  PLETCHER, Nathan, M. ,  ZHAO, Yu ,  MYERS, Thomas, A.

Inventor： HADJICHRISTOS, Aristotele ,  SEE, Puay Hoe ,  NEJATI, Babak ,  KLEMENS, Guy ,  FREDERICK, Norman, L., Jr. ,  SAHOTA, Gurkanwal, Singh ,  CASSIA, Marco ,  PLETCHER, Nathan, M. ,  ZHAO, Yu ,  MYERS, Thomas, A.

IPC: H04B1/04

CPC classification number: H04B1/0458 ,  H03F1/0277 ,  H03F3/24 ,  H03F3/72 ,  H03F2203/7236 ,  H04B1/0483

Abstract: A multi-mode multi-band power amplifier (PA) module is described. In an exemplary design, the PA module includes multiple power amplifiers, multiple matching circuits, and a set of switches. Each power amplifier provides power amplification for its input signal when selected. Each matching circuit provides impedance matching and filtering for its power amplifier and provides a respective output signal. The switches configure the power amplifiers to support multiple modes, with each mode being for a particular radio technology. Each power amplifier supports at least two modes. The PA module may further include a driver amplifier and an additional matching circuit. The driver amplifier amplifies an input signal and provides an amplified signal to the power amplifiers. The additional matching circuit combines the outputs of other matching circuits and provides an output signal with higher output power. The driver amplifier and the power amplifiers can support multiple output power levels.

Abstract translation: 描述了多模式多频带功率放大器（PA）模块。 在示例性设计中，PA模块包括多个功率放大器，多个匹配电路和一组开关。 每个功率放大器在选择时为其输入信号提供功率放大。 每个匹配电路为其功率放大器提供阻抗匹配和滤波，并提供相应的输出信号。 这些开关配置功率放大器以支持多种模式，每种模式用于特定的无线电技术。 每个功率放大器支持至少两种模式。 PA模块还可以包括驱动器放大器和附加匹配电路。 驱动器放大器放大输入信号并向功率放大器提供放大的信号。 附加匹配电路组合其他匹配电路的输出，并提供具有较高输出功率的输出信号。 驱动器放大器和功率放大器可以支持多个输出功率电平。

公开(公告)号：WO2009061838A1

公开(公告)日：2009-05-14

申请号：PCT/US2008/082507

申请日：2008-11-05

Applicant: QUALCOMM Incorporated ,  CASSIA, Marco ,  HADJICHRISTOS, Aristotele

Inventor： CASSIA, Marco ,  HADJICHRISTOS, Aristotele

IPC: H04B1/04

CPC classification number: H04B1/0475 ,  H03F1/02 ,  H03F1/0244 ,  H03F3/24 ,  H03F3/45475 ,  H03F2203/45731 ,  H04B1/0057 ,  H04B1/406 ,  H04B2001/045

Abstract: Switchable voltage level supplies for circuitry in a multi-mode communications chipset are disclosed. In an embodiment, a first voltage level is supplied to TX circuitry operating in a first mode having a first set of linearity and/or noise requirements. A second voltage level lower than the first voltage level is supplied to TX circuitry operating in a second mode having a second set of linearity and/or noise requirements looser than the first set of requirements. The first mode may be operation according to the GSM standard, and the second mode may be operation according to the W-CDMA standard.

Abstract translation: 公开了一种用于多模式通信芯片组中的电路的可切换电压电平。 在一个实施例中，向具有第一组线性和/或噪声要求的第一模式工作的TX电路提供第一电压电平。 低于第一电压电平的第二电压电平被提供给具有比第一组要求松动的第二组线性和/或噪声要求的第二模式工作的TX电路。 第一模式可以是根据GSM标准的操作，并且第二模式可以是根据W-CDMA标准的操作。