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    SYNCHRONIZATION OF INTERRUPT PROCESSING TO REDUCE POWER CONSUMPTION
    2.
    发明申请
    SYNCHRONIZATION OF INTERRUPT PROCESSING TO REDUCE POWER CONSUMPTION 审中-公开
    中断处理同步降低功耗

    公开(公告)号：WO2015143594A8

    公开(公告)日：2016-08-04

    申请号：PCT/CN2014073926

    申请日：2014-03-24

    Applicant: INTEL CORP ,  LOH THIAM WAH ,  CHINYA GAUTHAM N ,  HAMMARLUND PER ,  FORTAS REZA ,  WANG HONG ,  SUN HUAJIN

    Inventor： LOH THIAM WAH ,  CHINYA GAUTHAM N ,  HAMMARLUND PER ,  FORTAS REZA ,  WANG HONG ,  SUN HUAJIN

    IPC: G06F13/24

    CPC classification number: G06F13/24 ,  G06F2213/2404 ,  G06F2213/2406 ,  Y02D10/14

    Abstract: A processor is disclosed and includes at least one core including a first core, and interrupt delay logic. The interrupt delay logic is to receive a first interrupt at a first time and delay the first interrupt from being processed by a first time delay that begins at the first time,unless the first interrupt is pending at a second time when a second interrupt is processed by the first core. If the first interrupt is pending at the second time,the interrupt delay logic is to indicate to the first core to begin to process the first interrupt prior to completion of the first time delay. Other embodiments are disclosed and claimed.

    Abstract translation: 公开了一种处理器，并且包括至少一个包括第一核心和中断延迟逻辑的核心。 中断延迟逻辑是在第一时间接收第一个中断，并延迟第一个中断从第一个时间开始的第一个时间延迟处理，除非第一个中断在第二个中断处理时处于待机状态 由第一核心。 如果第二次中断第一次中断，中断延迟逻辑将在第一个时间延迟完成之前指示第一个内核开始处理第一个中断。 公开和要求保护其他实施例。

    METHOD AND APPARATUS FOR SPECULATIVE EXECUTION OF UNCONTENDED LOCK INSTRUCTIONS
    3.
    发明申请
    METHOD AND APPARATUS FOR SPECULATIVE EXECUTION OF UNCONTENDED LOCK INSTRUCTIONS 审中-公开
    用于未执行的锁定指令的执行的方法和装置

    公开(公告)号：WO2006012103A2

    公开(公告)日：2006-02-02

    申请号：PCT/US2005021838

    申请日：2005-06-17

    Applicant: INTEL CORP ,  SAHA BRATIN ,  MERTEN MATTHEW C ,  HAMMARLUND PER

    Inventor： SAHA BRATIN ,  MERTEN MATTHEW C ,  HAMMARLUND PER

    IPC: G06F9/00

    CPC classification number: G06F9/3004 ,  G06F9/30087 ,  G06F9/3834 ,  G06F9/3842

    Abstract: A method and apparatus for executing lock instructions speculatively in an out-of-order processor are disclosed. In one embodiment, a prediction is made whether a given lock instruction will actually be contended. If not, then the lock instruction may be treated as having a normal load micro-operation which may be speculatively executed. Monitor logic may look for indications that the lock instruction is actually contended. If no such indications are found, the speculative load micro-operation and other micro-operations corresponding to the lock instruction may retire. However, if such indications are in fact found, the lock instruction may be restarted, and the prediction mechanism may be updated.

    Abstract translation: 公开了一种在无序处理器中推测性地执行锁定指令的方法和设备。 在一个实施例中，预测给定的锁定指令是否实际上将被争用。 如果不是，则锁定指令可被视为具有可被推测执行的正常加载微操作。 监视逻辑可以查找锁指令实际上是否存在争用的指示。 如果没有找到这样的指示，则可以撤销对应于锁定指令的推测加载微操作和其他微操作。 但是，如果实际上发现了这样的指示，那么可以重新开始锁定指令，并且可以更新预测机制。

    RESCHEDULING MULTIPLE MICRO-OPERATIONS IN A PROCESSOR USING A REPLAY QUEUE
    7.
    发明申请
    RESCHEDULING MULTIPLE MICRO-OPERATIONS IN A PROCESSOR USING A REPLAY QUEUE 审中-公开
    使用REPLAY QUEUE对处理器中的多个微操作进行排序

    公开(公告)号：WO0242902A2

    公开(公告)日：2002-05-30

    申请号：PCT/US0151023

    申请日：2001-10-18

    Applicant: INTEL CORP ,  CARMEAN DOUGLAS M ,  BOGGS DARRELL D ,  SAGER DAVID J ,  MCKEEN FRANCIS X ,  HAMMARLUND PER ,  SINGHAL RONAK

    Inventor： CARMEAN DOUGLAS M ,  BOGGS DARRELL D ,  SAGER DAVID J ,  MCKEEN FRANCIS X ,  HAMMARLUND PER ,  SINGHAL RONAK

    IPC: G06F9/38 ,  G06F9/00

    CPC classification number: G06F9/3842 ,  G06F9/3861

    Abstract: Rescheduling multiple micro-operations in a processor using a replay queue. The processor comprises a replay queue to receive a plurality of instructions and an execution unit to execute the plurality of instructions. A scheduler is coupled between the replay queue and the execution unit. The scheduler speculatively schedules instructions for execution and dispatches each instruction to the execution unit. A checker is couple to the execution unit to determine whether each instruction has executed successfully. The checker is also coupled to the replay queue to communicate to the replay queue each instruction that has not executed successfully.

    Abstract translation: 使用重放队列在处理器中重新安排多个微操作。 处理器包括用于接收多个指令的重放队列和执行多个指令的执行单元。 调度器耦合在重播队列和执行单元之间。 调度器推测性地安排执行指令并将每个指令分派到执行单元。 检查器耦合到执行单元，以确定每个指令是否已成功执行。 检查器还耦合到重播队列，以便与未执行成功的每个指令通信给重播队列。

    SYNCRONIZATION OF INTERRUPT PROCESSING TO REDUCE POWER CONSUMPTION
    8.
    发明申请
    SYNCRONIZATION OF INTERRUPT PROCESSING TO REDUCE POWER CONSUMPTION 审中-公开
    中断处理同步减少功耗

    公开(公告)号：WO2015143594A1

    公开(公告)日：2015-10-01

    申请号：PCT/CN2014/073926

    申请日：2014-03-24

    Applicant: INTEL CORPORATION ,  LOH, Thiam Wah ,  CHINYA, Gautham N. ,  HAMMARLUND, Per ,  FORTAS, Reza ,  WANG, Hong ,  SUN, Huajin

    Inventor： LOH, Thiam Wah ,  CHINYA, Gautham N. ,  HAMMARLUND, Per ,  FORTAS, Reza ,  WANG, Hong ,  SUN, Huajin

    IPC: G06F13/24

    CPC classification number: G06F13/24 ,  G06F2213/2404 ,  G06F2213/2406 ,  Y02D10/14

    Abstract: A processor is disclosed and includes at least one core including a first core, and interrupt delay logic. The interrupt delay logic is to receive a first interrupt at a first time and delay the first interrupt from being processed by a first time delay that begins at the first time,unless the first interrupt is pending at a second time when a second interrupt is processed by the first core. If the first interrupt is pending at the second time,the interrupt delay logic is to indicate to the first core to begin to process the first interrupt prior to completion of the first time delay. Other embodiments are disclosed and claimed.

    Abstract translation: 公开了一种处理器，并且包括至少一个包括第一内核和中断延迟逻辑的核心。 中断延迟逻辑是在第一时间接收第一个中断并且延迟第一个中断被处理的第一个时间延迟开始于第一个时间，除非第一个中断在第二个中断处理时处于第二个中断 由第一核心。 如果第二次中断第一次中断，中断延迟逻辑将在第一个时间延迟完成之前指示第一个内核开始处理第一个中断。 公开和要求保护其他实施例。

    DECOUPLING THE NUMBER OF LOGICAL THREADS FROM THE NUMBER OF SIMULTANEOUS PHYSICAL THREADS IN A PROCESSOR
    10.
    发明申请
    DECOUPLING THE NUMBER OF LOGICAL THREADS FROM THE NUMBER OF SIMULTANEOUS PHYSICAL THREADS IN A PROCESSOR 审中-公开
    从处理器中同时存在的多个物理线程中去除逻辑线程的数量

    公开(公告)号：WO2006057647A3

    公开(公告)日：2006-07-20

    申请号：PCT/US2004043036

    申请日：2004-12-20

    Applicant: INTEL CORP ,  HAMMARLUND PER ,  FARCY ALEXANDRE ,  MARDEN MORRIS ,  CARMEAN DOUGLAS ,  MICHAUD PIERRE ,  HINTON ROBERT

    Inventor： HAMMARLUND PER ,  FARCY ALEXANDRE ,  MARDEN MORRIS ,  CARMEAN DOUGLAS ,  MICHAUD PIERRE ,  HINTON ROBERT ,  JOURDAN STEPHAN

    IPC: G06F9/46 ,  G06F9/48 ,  G06F11/00

    CPC classification number: G06F9/485 ,  G06F9/3851

    Abstract: Systems and methods of managing threads provide for supporting a plurality of logical threads with a plurality of simultaneous physical threads in which the number of logical threads may be greater than or less than the number of physical threads. In one approach, each of the plurality of logical threads is maintained in one of a wait state, an active state, a drain state, and a stall state. A state machine and hardware sequencer can be used to transition the logical threads between states based on triggering events and whether or not an interruptible point has been encountered in the logical threads. The logical threads are scheduled on the physical threads to meet, for example, priority, performance or fairness goals. It is also possible to specify the resources that are available to each logical thread in order to meet these and other, goals. In one example, a single. logical thread can speculatively use more than one physical thread, pending a selection of which physical thread should be committed.

    Abstract translation: 管理线程的系统和方法提供支持具有多个同时物理线程的多个逻辑线程，其中逻辑线程的数量可以大于或小于物理线程的数量。 在一种方法中，多个逻辑线程中的每一个保持在等待状态，活动状态，排出状态和停转状态之一。 可以使用状态机和硬件定序器基于触发事件以及逻辑线程中是否遇到可中断点来转换状态之间的逻辑线程。 逻辑线程在物理线程上进行调度，以满足例如优先级，性能或公平目标。 也可以指定每个逻辑线程可用的资源，以满足这些和其他目标。 在一个例子中，一个单一的。 逻辑线程可以推测性地使用多个物理线程，等待选择哪个物理线程应该提交。

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