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    METHODS OF CONDUCTING WAFER LEVEL BURN-IN OF ELECTRONIC DEVICES
    4.
    发明申请
    METHODS OF CONDUCTING WAFER LEVEL BURN-IN OF ELECTRONIC DEVICES 审中-公开
    导电水平电子装置的方法

    公开(公告)号：WO03017326A3

    公开(公告)日：2003-05-15

    申请号：PCT/US0225640

    申请日：2002-08-12

    Applicant: HONEYWELL INT INC ,  HAJI-SHEIKH MICHAEL J ,  BIARD JAMES R ,  HAWKINS ROBERT M ,  RABINOVICH SIMON ,  GUENTER JAMES K

    Inventor： HAJI-SHEIKH MICHAEL J ,  BIARD JAMES R ,  HAWKINS ROBERT M ,  RABINOVICH SIMON ,  GUENTER JAMES K

    IPC: H01L21/66 ,  G01R31/27 ,  G01R31/28 ,  H01S5/042 ,  H01S5/183 ,  H01S5/42 ,  G01R31/316

    CPC classification number: G01R31/275 ,  G01R31/2831 ,  G01R31/2863 ,  G01R31/2872 ,  G01R31/2874 ,  G01R31/2884 ,  H01S5/0021 ,  H01S5/005 ,  H01S5/423

    Abstract: Methods of conducting wafer level burn-in (WLBI) of semiconductor devices are presented wherein systems are provided having at least two electrodes (210, 215). Electrical bias (920) and/or thermal power (925) is applied on each side of a wafer (100) having back and front electrical contacts for semiconductor devices borne by the wafer. A pliable conductive layer (910) is described for supplying pins on the device side of a wafer with electrical contact and/or also for providing protection to the wafer from mechanical pressure being applied to its surfaces. Use of a cooling system (950) is also described for enabling the application of a uniform temperature to a wafer undergoing burn-in. Wafer level burn-in is performed by applying electrical and physical contact (915) using an upper contact plate to individual contacts for the semiconductor devices ; applying electrical and physical contact using a lower contact plate (910) to a substrate surface of said semiconductor wafer ; providing electrical power (920) to said semiconductor devices through said upper and lower second contact plates from a power source coupled to said upper and lower contacts plates ; monitoring and controlling electrical power (935) to said semiconductor devices for a period in accordance with a specified burn-in criteria ; removing electrical power at completion of said period (955) ; and removing electrical and physical contact to said semiconductor wafer (965).

    Abstract translation: 提供了进行半导体器件的晶片级老化（WLBI）的方法，其中提供具有至少两个电极（210,215）的系统。 电晶体（920）和/或热功率（925）施加在具有由晶片承载的半导体器件的背面和前部电触点的晶片（100）的每一侧上。 描述了一种柔性导电层（910），用于在具有电接触的晶片的器件侧上提供引脚和/或用于为施加到其表面的机械压力提供对晶片的保护。 还描述了使用冷却系统（950），以使得能够对经历老化的晶片施加均匀的温度。 通过使用上接触板向半导体器件的单个触点施加电和物理接触（915）来执行晶片级老化; 使用下接触板（910）将电和物理接触施加到所述半导体晶片的衬底表面; 通过所述上和下第二接触板从耦合到所述上和下接触板的电源向所述半导体器件提供电力（920）; 根据指定的老化标准对所述半导体器件监测和控制电力（935）一段时间; 在所述期间完成时移除电力（955）; 以及去除与所述半导体晶片（965）的电和物理接触。

    PROVIDING CURRENT CONTROL OVER WAFER BORNE SEMICONDUCTOR DEVICES USING OVERLAYER PATTERNS
    5.
    发明申请
    PROVIDING CURRENT CONTROL OVER WAFER BORNE SEMICONDUCTOR DEVICES USING OVERLAYER PATTERNS 审中-公开
    利用覆盖层模式在晶圆转子半导体器件上提供电流控制

    公开(公告)号：WO2003017352A2

    公开(公告)日：2003-02-27

    申请号：PCT/US2002/025648

    申请日：2002-08-12

    Applicant: HONEYWELL INTERNATIONAL INC. ,  HAJI-SHEIKH, Michael, J. ,  BIARD, James, R. ,  HAWKINS, Robert, M. ,  GUENTER, James, K.

    Inventor： HAJI-SHEIKH, Michael, J. ,  BIARD, James, R. ,  HAWKINS, Robert, M. ,  GUENTER, James, K.

    IPC: H01L21/66

    CPC classification number: G01R31/275 ,  G01R31/2831 ,  G01R31/2863 ,  G01R31/2872 ,  G01R31/2874 ,  G01R31/2884 ,  H01S5/0021 ,  H01S5/005 ,  H01S5/423

    Abstract: Disclosed are methods for providing wafer parasitic current control to a semiconductor wafer (1240) having a substrate (1240), at least one active layer (1240) and at least one surface layer (1240), Current control can be achieved through the formation of patterns ( 1240) surrounding contacts (1215), said patterns (1240) including insulating implants and/or sacrificial layers formed between active devices represented by said contacts (1215). Current flows through active regions (1260) associated with said contacts (1215) and active devices. Methods of and systems for wafer level burn-in (WLBI) of semiconductor devices are also disclosed. Current control at the wafer level is important when using WLBI methods and systems.

    Abstract translation: 公开了用于向具有衬底（1240），至少一个有源层（1240）和至少一个表面层（1240）的半导体晶片（1240）提供晶片寄生电流控制的方法，电流 可以通过形成围绕触点（1215）的图案（1240）来实现控制，所述图案（1240）包括在由所述触点（1215）表示的有源器件之间形成的绝缘注入物和/或牺牲层。 电流流过与所述触点（1215）和有源器件相关联的有源区域（1260）。 还公开了用于半导体器件的晶片级老化（WLBI）的方法和系统。 在使用WLBI方法和系统时，晶圆级的电流控制很重要。

    METHODS OF CONDUCTING WAFER LEVEL BURN-IN OF ELECTRONIC DEVICES
    7.
    发明申请
    METHODS OF CONDUCTING WAFER LEVEL BURN-IN OF ELECTRONIC DEVICES 审中-公开
    电子器件引起晶片电平烧毁的方法

    公开(公告)号：WO2003017326A2

    公开(公告)日：2003-02-27

    申请号：PCT/US2002/025640

    申请日：2002-08-12

    Applicant: HONEYWELL INTERNATIONAL INC. ,  HAJI-SHEIKH, Michael, J. ,  BIARD, James, R. ,  HAWKINS, Robert, M. ,  RABINOVICH, Simon ,  GUENTER, James, K.

    Inventor： HAJI-SHEIKH, Michael, J. ,  BIARD, James, R. ,  HAWKINS, Robert, M. ,  RABINOVICH, Simon ,  GUENTER, James, K.

    IPC: H01L

    CPC classification number: G01R31/275 ,  G01R31/2831 ,  G01R31/2863 ,  G01R31/2872 ,  G01R31/2874 ,  G01R31/2884 ,  H01S5/0021 ,  H01S5/005 ,  H01S5/423

    Abstract: Methods of conducting wafer level burn-in (WLBI) of semiconductor devices are presented wherein systems are provided having at least two electrodes (210, 215). Electrical bias (920) and/or thermal power (925) is applied on each side of a wafer (100) having back and front electrical contacts for semiconductor devices borne by the wafer. A pliable conductive layer (910) is described for supplying pins on the device side of a wafer with electrical contact and/or also for providing protection to the wafer from mechanical pressure being applied to its surfaces. Use of a cooling system (950) is also described for enabling the application of a uniform temperature to a wafer undergoing burn-in. Wafer level burn-in is performed by applying electrical and physical contact (915) using an upper contact plate to individual contacts for the semiconductor devices ; applying electrical and physical contact using a lower contact plate (910) to a substrate surface of said semiconductor wafer ; providing electrical power (920) to said semiconductor devices through said upper and lower second contact plates from a power source coupled to said upper and lower contacts plates ; monitoring and controlling electrical power (935) to said semiconductor devices for a period in accordance with a specified burn-in criteria ; removing electrical power at completion of said period (955) ; and removing electrical and physical contact to said semiconductor wafer (965).

    Abstract translation: 介绍了进行半导体器件的晶圆级预烧（WLBI）的方法，其中提供了具有至少两个电极（210,215）的系统。 在晶片（100）的每一侧上施加电偏压（920）和/或热功率（925），该晶片具有由晶片承载的半导体器件的前后电触点。 描述了柔性导电层（910）用于通过电接触在晶片的器件侧上提供引脚，和/或还用于通过施加到其表面的机械压力来为晶片提供保护。 还描述了冷却系统（950）的使用，以使得能够对经历烧入的晶片施加均匀的温度。 通过使用上接触板对半导体器件的单个触点施加电和物理接触（915）来执行晶片级别老化; 使用下接触板（910）将电接触和物理接触施加到所述半导体晶片的衬底表面; 通过所述上部和下部第二接触板从耦合到所述上部和下部接触板的电源向所述半导体器件提供电力（920） 根据指定的老化标准在一段时间内监测和控制电力（935）到所述半导体器件; 在所述时间段结束时去除电力（955）; 并去除与所述半导体晶片（965）的电和物理接触。

    SYSTEMS FOR WAFER LEVEL BURN-IN OF ELECTRONIC DEVICES
    8.
    发明申请
    SYSTEMS FOR WAFER LEVEL BURN-IN OF ELECTRONIC DEVICES 审中-公开

    公开(公告)号：WO2003017335A3

    公开(公告)日：2003-02-27

    申请号：PCT/US2002/025664

    申请日：2002-08-12

    Applicant: HONEYWELL INTERNATIONAL INC. ,  HAJI-SHEIKH, Michael, J. ,  BIARD, James, R. ,  HAWKINS, Robert, M. ,  RABINOVICH, Simon ,  GUENTER, James, K.

    Inventor： HAJI-SHEIKH, Michael, J. ,  BIARD, James, R. ,  HAWKINS, Robert, M. ,  RABINOVICH, Simon ,  GUENTER, James, K.

    IPC: G01R21/316

    Abstract: Systems for wafer level burn-in (WLBI) of semiconductor devices (210, 215) are presented. Systems having at least two electrodes for the application of electrical bias and/or thermal power on each side of a wafer (100) having back (105) and front (110) electrical contacts for semiconductor devices borne by the wafer (100) is described. Methods of wafer level burnin using the system are also described. Furthermore, a pliable conductive layer (220) is described for supplying pins or contacts (110) on device side of a wafer with electrical contact. The pliable conductive layer (220) can allow for an effective series R in each of the devices borne by the wafer (100), thus helping keep voltage bias level consistent. The pliable conductive layer can also prevent damage to a wafer when pressure is applied to it by chamber contacts (210, 215) and pressure onto surfaces of the wafer (100) during burn-in operations. A cooling system (660) is also described for enabling the application of a uniform temperature to the wafer (100) undergoing burn-in.

    SYSTEMS FOR WAFER LEVEL BURN-IN OF ELECTRONIC DEVICES
    9.
    发明申请
    SYSTEMS FOR WAFER LEVEL BURN-IN OF ELECTRONIC DEVICES 审中-公开
    用于电子设备的水平电平的系统

    公开(公告)号：WO2003017335A2

    公开(公告)日：2003-02-27

    申请号：PCT/US2002/025664

    申请日：2002-08-12

    Applicant: HONEYWELL INTERNATIONAL INC. ,  HAJI-SHEIKH, Michael, J. ,  BIARD, James, R. ,  HAWKINS, Robert, M. ,  RABINOVICH, Simon ,  GUENTER, James, K.

    Inventor： HAJI-SHEIKH, Michael, J. ,  BIARD, James, R. ,  HAWKINS, Robert, M. ,  RABINOVICH, Simon ,  GUENTER, James, K.

    IPC: H01L21/00

    CPC classification number: G01R31/275 ,  G01R31/2831 ,  G01R31/2863 ,  G01R31/2872 ,  G01R31/2874 ,  G01R31/2884 ,  H01S5/0021 ,  H01S5/005 ,  H01S5/423

    Abstract: Systems for wafer level burn-in (WLBI) of semiconductor devices (210, 215) are presented. Systems having at least two electrodes for the application of electrical bias and/or thermal power on each side of a wafer (100) having back (105) and front (110) electrical contacts for semiconductor devices borne by the wafer (100) is described. Methods of wafer level burnin using the system are also described. Furthermore, a pliable conductive layer (220) is described for supplying pins or contacts (110) on device side of a wafer with electrical contact. The pliable conductive layer (220) can allow for an effective series R in each of the devices borne by the wafer (100), thus helping keep voltage bias level consistent. The pliable conductive layer can also prevent damage to a wafer when pressure is applied to it by chamber contacts (210, 215) and pressure onto surfaces of the wafer (100) during burn-in operations. A cooling system (660) is also described for enabling the application of a uniform temperature to the wafer (100) undergoing burn-in.

    Abstract translation: 提出了用于半导体器件（210,215）的晶片级老化（WLBI）的系统。 描述具有至少两个电极的系统，用于在具有由晶片（100）承载的半导体器件的背面（105）和前（110）电触点的晶片（100）的每一侧上施加电偏压和/或热功率。 。 还描述了使用该系统的晶片级烧伤的方法。 此外，描述了用于在具有电接触的晶片的器件侧上提供引脚或触点（110）的柔性导电层（220）。 柔性导电层（220）可以允许由晶片（100）承载的每个器件中的有效串联R，从而有助于保持电压偏置电平一致。 柔性导电层还可以防止在老化操作期间通过室接触（210,215）向其施加压力和施加到晶片（100）的表面上的压力时对晶片的损坏。 还描述了一种冷却系统（660），用于使得能够对经历老化的晶片（100）施加均匀的温度。

    PROVIDING CURRENT CONTROL OVER WAFER BORNE SEMICONDUCTOR DEVICES USING TRENCHES
    10.
    发明申请
    PROVIDING CURRENT CONTROL OVER WAFER BORNE SEMICONDUCTOR DEVICES USING TRENCHES 审中-公开
    通过使用TRENCHES的波形BORNE半导体器件提供电流控制

    公开(公告)号：WO03017325A2

    公开(公告)日：2003-02-27

    申请号：PCT/US0225639

    申请日：2002-08-12

    Applicant: HONEYWELL INT INC ,  HAJI-SHEIKH MICHAEL J ,  BIARD JAMES R ,  HAWKINS ROBERT M ,  GUENTER JAMES K

    Inventor： HAJI-SHEIKH MICHAEL J ,  BIARD JAMES R ,  HAWKINS ROBERT M ,  GUENTER JAMES K

    IPC: H01L21/66 ,  G01R31/27 ,  G01R31/28 ,  H01S5/042 ,  H01S5/183 ,  H01S5/42 ,  H01L

    CPC classification number: G01R31/275 ,  G01R31/2831 ,  G01R31/2863 ,  G01R31/2872 ,  G01R31/2874 ,  G01R31/2884 ,  H01S5/0021 ,  H01S5/005 ,  H01S5/423

    Abstract: Disclosed are methods for providing wafer parasitic current control to a semiconductor wafer (1500) having a substrate (1520), at least one active layer (1565) and a surface layer (1510), and electrical contacts (1515) formed on said surface layer (1510). Current control can be achieved with the formation of trenches (1525) around electrical contacts, where electrical contacts and associated layers define an electronic device. Insulating implants (1530) can be placed into trenches (1525) and/or sacrificial layers (1540) can be formed between electronic contacts (1515). Trenches control current by promoting current flow within active (e.g., conductive) regions (1560) and impeding current flow through inactive (e.g., nonconductive) regions (1550). Methods of and systems for wafer level burn-in (WLBI) of semiconductor devices are also disclosed. Current control at the wafer level is important when using WLBI methods and systems.

    Abstract translation: 公开了一种用于向具有衬底（1520），至少一个有源层（1565）和表面层（1510）的半导体晶片（1500）提供晶片寄生电流控制的方法以及形成在所述表面层上的电触头（1515） （1510）。 可以通过在电触点周围形成沟槽（1525）来实现电流控制，其中电触点和相关层限定电子装置。 绝缘植入物（1530）可以放置在沟槽（1525）中，并且可以在电子触点（1515）之间形成牺牲层（1540）。 沟槽通过促进在有源（例如，导电）区域（1560）内的电流流动并阻止电流通过非活性（例如非导电）区域（1550）来控制电流。 还公开了半导体器件的晶片级老化（WLBI）的方法和系统。 使用WLBI方法和系统时，晶圆级的电流控制很重要。

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