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    Semiconductor device and fabrication method therefor
    5.
    发明申请
    Semiconductor device and fabrication method therefor 有权
    半导体器件及其制造方法

    公开(公告)号：US20040248362A1

    公开(公告)日：2004-12-09

    申请号：US10777704

    申请日：2004-02-13

    Applicant: ELPIDA MEMORY, INC. ,  Hitachi ULSI Systems, Co., Ltd. ,  HITACHI LTD.

    Inventor： Yoshitaka Nakamura ,  Hidekazu Goto ,  Isamu Asano ,  Mitsuhiro Horikawa ,  Keiji Kuroki ,  Hiroshi Sakuma ,  Kenichi Koyanagi ,  Tsuyoshi Kawagoe

    IPC: H01L021/8242 ,  H01L029/76

    CPC classification number: H01L28/65 ,  H01L21/7687 ,  H01L27/10814 ,  H01L27/10852

    Abstract: A semiconductor device includes memory cells each having an MISFET for memory selection formed on one major surface of a semiconductor substrate and a capacitive element comprised of a lower electrode electrically connected at a bottom portion to one of a source and drain of the MISFET for memory selection via a first metal layer and an upper electrode formed on the lower electrode via a capacitive insulating film. The lower electrode has a thickness of 30 nm or greater at the bottom portion thereof. Sputtering with a high ionization ratio and high directivity, such as PCM, is adapted to the formation of the lower electrode to make only the bottom portion of a capacitor thicker.

    Abstract translation: 一种半导体器件包括各自具有形成在半导体衬底的一个主表面上的用于存储器选择的MISFET的存储单元，以及由用于存储器选择的MISFET的源极和漏极的底部电连接到下部电极的电容元件 经由电容绝缘膜经由形成在下电极上的第一金属层和上电极。 下部电极的底部的厚度为30nm以上。 具有高电离比和高方向性的溅射（例如PCM）适于形成下电极，以使电容器的底部仅较厚。

    Level shift circuit and semiconductor integrated circuit
    6.
    发明申请
    Level shift circuit and semiconductor integrated circuit 失效
    电平移位电路和半导体集成电路

    公开(公告)号：US20040227558A1

    公开(公告)日：2004-11-18

    申请号：US10872539

    申请日：2004-06-22

    Applicant: Renesas Technology Corp. ,  Hitachi ULSI Systems Co., Ltd.

    Inventor： Hirokatsu Hayashi ,  Toshiro Takahashi

    IPC: G11C011/34

    CPC classification number: H03K19/00323

    Abstract: In a conventional level conversion circuit, the variation of output signals from a low level to a high level is slower than that from a high level to a low level. As a consequence, on the part of a circuit receiving signals from such a level conversion circuit, signals have to be accepted at the later signal timing, resulting in the problems of more complex timing design and of a longer time taken by signal transmission, which impedes raising the system speed. The configuration is such that a level conversion circuit is composed of a level shift circuit for supplying a level-converted signal in the same phase as the input signal and a signal in the reverse phase thereto and a follow-up circuit responsive to the earlier of the output signals of the level shift circuit for generating an output signal, wherein the follow-up circuit consists of an inverter circuit in which two p-channel type MOS transistors and two n-channel type MOS transistors are connected in series between a first voltage terminal and a second voltage terminal, of which one pair is used as input transistors and the remaining pair of transistors are subjected to feedback based on the output signal of the level shift circuit to be quickly responsive to the next variation.

    Abstract translation: 在传统的电平转换电路中，从低电平到高电平的输出信号的变化比从高电平到低电平的输出信号的变化慢。 因此，在接收来自这种电平转换电路的信号的电路中，必须在稍后的信号定时处接收信号，导致更复杂的定时设计和信号传输所花费的时间更长的问题， 阻碍提高系统速度。 该配置使得电平转换电路由电平移位电路组成，电平移位电路用于提供与输入信号相同相位的电平转换信号和与其相反的信号，以及响应于较早 用于产生输出信号的电平移位电路的输出信号，其中后续电路由两个p沟道型MOS晶体管和两个n沟道型MOS晶体管串联连接在第一电压 端子和第二电压端子，其中一对用作输入晶体管，并且剩余的一对晶体管基于电平移位电路的输出信号进行反馈，以快速响应下一个变化。

    Semiconductor memory device
    7.
    发明申请
    Semiconductor memory device 失效
    半导体存储器件

    公开(公告)号：US20040156259A1

    公开(公告)日：2004-08-12

    申请号：US10633710

    申请日：2003-08-05

    Applicant: ELPIDA MEMORY, INC ,  HITACHI ULSI SYSTEMS, CO., LTD. ,  HITACHI, LTD.

    Inventor： Kouichiro Ninomiya ,  Isamu Fujii ,  Hiroki Fujisawa

    IPC: G11C008/00

    CPC classification number: G11C8/08 ,  G11C8/14 ,  G11C11/4085

    Abstract: A semiconductor memory device is capable of performing a faster operation by reducing a load applied to a subword selection line or driving a subword driver provided for each memory mat. In a drive method of subword drivers that are actuated in response to subword selection signals supplied through subword selection lines, the subword selection lines are branched according to the number of memory mats. Each subword selection signal has a polarity to a branching position and an inverted polarity from each branching position to each subword driver. The inverted subword selection signal together with a main word signal are calculated to operation in each subword driver and output as a subword drive signal. The plurality of subword drivers share an inverter circuit for inverting the main word signals so as to permit a simplified circuit configuration.

    Abstract translation: 半导体存储器件能够通过减小施加到子选择线的负载或驱动为每个存储器垫提供的子字驱动器来执行更快的操作。 在响应于通过子选择线提供的子字选择信号被致动的子字驱动器的驱动方法中，子字选择线根据存储器数的数量被分支。 每个子字选择信号具有分支位置的极性和从每个分支位置到每个子字驱动器的反相极性。 计算出反相子字选择信号与主字信号一起在每个子字驱动器中的操作，并作为子字驱动信号输出。 多个子字驱动器共享用于反转主字信号的逆变器电路，以便允许简化的电路配置。

    Insulated gate field effect transistor and method of fabricating the same
    8.
    发明申请
    Insulated gate field effect transistor and method of fabricating the same 审中-公开
    绝缘栅场效应晶体管及其制造方法

    公开(公告)号：US20040132241A1

    公开(公告)日：2004-07-08

    申请号：US10740678

    申请日：2003-12-22

    Applicant: HITACHI, LTD. ,  HITACHI ULSI SYSTEMS CO., LTD.

    Inventor： Masatada Horiuchi ,  Takashi Takahama

    IPC: H01L021/8238

    CPC classification number: H01L21/2652 ,  H01L21/2658 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/1045 ,  H01L29/1083 ,  H01L29/6659 ,  H01L29/66659 ,  H01L29/7833

    Abstract: A first object of the present invention is to provide an insulated gate field effect transistor which realizes reductions in the junction depth and the resistance of source and drain junction regions beneath a gate electrode. Another object is to provide a miniaturized complementary type insulated gate field effect transistor capable of achieving a large current and a high operation speed. In a miniaturized MOS transistor, a low concentration impurity integrated layer comprising In or Ga is provided so as to have a peak in the inside of high concentration shallow source and drain diffusion layer regions. By this arrangement, the shallow source and drain diffusion layers are attracted by the impurity integrated layer, to realize shallower junctions having a high concentration and a rectangular distribution. As a result, particularly, a miniaturized PMOS with a larger current punch-through hard and an ultra miniaturized configuration is achieved, and this can be applied also to NMOS, and, therefore, a CMOS with a larger current, punch-through hard and a more miniaturized configuration can be achieved without complicating the fabrication steps, namely, economically.

    Abstract translation: 本发明的第一个目的是提供一种绝缘栅场效应晶体管，其实现了栅极电极下面的源极和漏极结区域的结深度和电阻的减小。 另一个目的是提供能够实现大电流和高操作速度的小型化互补型绝缘栅场效应晶体管。 在小型化MOS晶体管中，设置包含In或Ga的低浓度杂质一体化层，使其在高浓度浅源极和漏极扩散层区域的内部具有峰值。 通过这种布置，浅源极和漏极扩散层被杂质集成层吸引，以实现具有高浓度和矩形分布的较浅结。 结果，特别地，实现了具有更大电流穿透硬化和超小型化配置的小型化PMOS，并且这也可以应用于NMOS，因此也可以应用于具有较大电流，穿透硬化和 可以在不使制造步骤复杂化的情况下，即经济地实现更小型化的构造。

    Address-counter control system
    9.
    发明申请
    Address-counter control system 失效
    地址对照控制系统

    公开(公告)号：US20040062128A1

    公开(公告)日：2004-04-01

    申请号：US10669303

    申请日：2003-09-24

    Applicant: Elpida Memory, Inc. ,  Hitachi ULSI Systems Co., Ltd. ,  Hitachi, Ltd.

    Inventor： Tomoyuki Inaba ,  Kiyoshi Nakai ,  Hideaki Kato

    IPC: G11C008/00

    CPC classification number: G11C8/04

    Abstract: An address-counter control system includes a counter circuit, path switches, and a control circuit. The counter circuit includes a first series of address counters which corresponds to a non-contiguous region portion and second and third series of address counters which correspond to respective contiguous region portions and which are located at two opposite ends of the first series of address counters. The path switches are provided at connection paths between the second and the third series of address counters. The path switches disconnect the first series of address counters and directly connect the second and third series of address counters or disconnect the direct connection between the second and third series of address counters and connect the first series of address counters to and between the second and the third series of address counters. The control circuit control the path switches.

    Abstract translation: 地址计数器控制系统包括计数器电路，路径开关和控制电路。 计数器电路包括对应于不连续区域部分的第一系列地址计数器和对应于相应连续区域部分并且位于第一系列地址计数器的两个相对端处的第二和第三系列地址计数器。 在第二和第三系列地址计数器之间的连接路径处提供路径切换。 路径开关断开第一系列地址计数器，并直接连接第二和第三系列地址计数器，或断开第二和第三系列地址计数器之间的直接连接，并将第一系列地址计数器连接到第二和第二 第三系列地址柜台。 控制电路控制路径开关。

    System and method for using dynamic random access memory and flash memory
    10.
    发明申请
    System and method for using dynamic random access memory and flash memory 有权
    使用动态随机存取存储器和闪存的系统和方法

    公开(公告)号：US20040049629A1

    公开(公告)日：2004-03-11

    申请号：US10445922

    申请日：2003-05-28

    Applicant: Hitachi, Ltd. ,  Hitachi ULSI Systems Co., Ltd.

    Inventor： Seiji Miura ,  Kazushige Ayukawa ,  Tetsuya Iwamura

    IPC: G06F012/00

    CPC classification number: G06F11/1068 ,  G06F12/0638 ,  Y02D10/13

    Abstract: A system and method are provided for using dynamic random access memory and flash memory. In one example, the memory system comprises a nonvolatile memory; synchronous dynamic random access memories; circuits including a control circuit which is coupled with the nonvolatile memory and the synchronous dynamic random access memories, and controls accesses to the nonvolatile memory and the synchronous dynamic random access memories; and a plurality of input/output terminals coupled with the circuits, wherein in data transfer from the nonvolatile memory to the synchronous dynamic random access memories, error corrected data is transferred.

    Abstract translation: 提供了一种使用动态随机存取存储器和闪速存储器的系统和方法。 在一个示例中，存储器系统包括非易失性存储器; 同步动态随机存取存储器; 包括与非易失性存储器和同步动态随机存取存储器耦合的控制电路的电路，并且控制对非易失性存储器和同步动态随机存取存储器的访问; 以及与电路耦合的多个输入/输出端子，其中在从非易失性存储器到同步动态随机存取存储器的数据传输中，传送纠错数据。

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