公开(公告)号：WO2008057837A1

公开(公告)日：2008-05-15

申请号：PCT/US2007/082884

申请日：2007-10-29

Applicant: INTEL CORPORATION ,  HE, Jun ,  LEE, Kevin, J. ,  GADRE, Kaustubh, S. ,  JOSHI, Sabhash, M.

Inventor： HE, Jun ,  LEE, Kevin, J. ,  GADRE, Kaustubh, S. ,  JOSHI, Sabhash, M.

IPC: H01L21/60 ,  H01L23/48

CPC classification number: H01L23/525 ,  H01L21/76834 ,  H01L21/76886 ,  H01L21/76888 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/0231 ,  H01L2224/02333 ,  H01L2224/0401 ,  H01L2224/05022 ,  H01L2224/05572 ,  H01L2224/114 ,  H01L2224/1147 ,  H01L2224/116 ,  H01L2224/11912 ,  H01L2224/13022 ,  H01L2224/13099 ,  H01L2224/13111 ,  H01L2224/13147 ,  H01L2924/0002 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01051 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10329 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2224/05552

Abstract: An integrated circuit apparatus comprises a semiconductor substrate having a plurality of devices formed thereon, one or more metallization layers to interconnect the plurality of devices, and a bond pad formed over the one or more metallization layers and electrically coupled to at least one of the metallization layers. A first passivation layer is formed over the bond pad and over the metallization layers and a redistribution interconnect formed on the passivation layer. A first via formed through the first passivation layer electrically couples the redistribution interconnect to the bond pad. A second passivation layer is formed on the redistribution interconnect to prevent thermomechanical degradation and improve electromigration performance. A dielectric layer is formed on the second passivation layer and a die-side bump is formed on the dielectric layer. A second via formed through the dielectric layer and through the second passivation layer electrically couples the die-side bump to the redistribution interconnect.

Abstract translation: 集成电路装置包括：半导体衬底，具有在其上形成的多个器件;一个或多个金属化层，用于互连多个器件;以及接合焊盘，形成在一个或多个金属化层上方， 耦合到至少一个金属化层。 第一钝化层形成在接合焊盘之上并且形成在钝化层上的金属化层和再分布互连上。 穿过第一钝化层形成的第一通孔将再分布互连件电耦合到键合焊盘。 在再分布互连上形成第二钝化层以防止热机械降解并提高电迁移性能。 在第二钝化层上形成电介质层，并在电介质层上形成管芯侧凸块。 形成穿过介电层并穿过第二钝化层的第二通孔将管芯侧凸块电耦合到重新分布互连。

公开(公告)号：WO2013048524A1

公开(公告)日：2013-04-04

申请号：PCT/US2011/054479

申请日：2011-10-01

Applicant: INTEL CORPORATION ,  PRADHAN, Sameer S. ,  JOSHI, Sabhash, M. ,  CHUN, Jin-Sung

Inventor： PRADHAN, Sameer S. ,  JOSHI, Sabhash, M. ,  CHUN, Jin-Sung

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L29/785 ,  H01L21/02 ,  H01L21/02532 ,  H01L21/283 ,  H01L21/28518 ,  H01L21/32053 ,  H01L21/76843 ,  H01L21/76855 ,  H01L21/76897 ,  H01L23/48 ,  H01L29/16 ,  H01L29/41791 ,  H01L29/456 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66666 ,  H01L29/66795 ,  H01L29/78 ,  H01L29/7851 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The present description relates to the field of fabricating microelectronic devices having non-planar transistors. Embodiments of the present description relate to the formation of source/drain contacts within non-planar transistors, wherein a titanium-containing contact interface may be used in the formation of the source/drain contact with a discreet titanium silicide formed between the titanium-containing interface and a silicon-containing source/drain structure.

Abstract translation: 本说明书涉及制造具有非平面晶体管的微电子器件的领域。 本发明的实施例涉及在非平面晶体管内形成源极/漏极接触，其中可以使用含钛接触界面来形成源极/漏极接触，其中形成在含钛的 界面和含硅源/排水结构。

公开(公告)号：WO2008057837A9

公开(公告)日：2008-07-03

申请号：PCT/US2007082884

申请日：2007-10-29

Applicant: INTEL CORP ,  HE JUN ,  LEE KEVIN J ,  GADRE KAUSTUBH S ,  JOSHI SABHASH M

Inventor： HE JUN ,  LEE KEVIN J ,  GADRE KAUSTUBH S ,  JOSHI SABHASH M

IPC: H01L21/60 ,  H01L23/48

CPC classification number: H01L23/525 ,  H01L21/76834 ,  H01L21/76886 ,  H01L21/76888 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/0231 ,  H01L2224/02333 ,  H01L2224/0401 ,  H01L2224/05022 ,  H01L2224/05572 ,  H01L2224/114 ,  H01L2224/1147 ,  H01L2224/116 ,  H01L2224/11912 ,  H01L2224/13022 ,  H01L2224/13099 ,  H01L2224/13111 ,  H01L2224/13147 ,  H01L2924/0002 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01051 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10329 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2224/05552

Abstract: An integrated circuit apparatus comprises a semiconductor substrate having a plurality of devices formed thereon, one or more metallization layers to interconnect the plurality of devices, and a bond pad formed over the one or more metallization layers and electrically coupled to at least one of the metallization layers. A first passivation layer is formed over the bond pad and over the metallization layers and a redistribution interconnect formed on the passivation layer. A first via formed through the first passivation layer electrically couples the redistribution interconnect to the bond pad. A second passivation layer is formed on the redistribution interconnect to prevent thermomechanical degradation and improve electromigration performance. A dielectric layer is formed on the second passivation layer and a die-side bump is formed on the dielectric layer. A second via formed through the dielectric layer and through the second passivation layer electrically couples the die-side bump to the redistribution interconnect.

Abstract translation: 集成电路装置包括具有形成在其上的多个器件的半导体衬底，用于互连多个器件的一个或多个金属化层以及形成在所述一个或多个金属化层上的接合焊盘，并且电连接至至少一个金属化层 层。 第一钝化层形成在接合焊盘上方和金属化层上方，以及形成在钝化层上的再分布互连。 通过第一钝化层形成的第一通孔将再分配互连电连接到接合焊盘。 在再分布互连上形成第二钝化层以防止热机械降解并改善电迁移性能。 在第二钝化层上形成电介质层，在电介质层上形成裸片侧凸点。 通过电介质层形成的第二通孔和通过第二钝化层电连接裸片侧凸起到再分布互连。