公开(公告)号：WO2004095245A2

公开(公告)日：2004-11-04

申请号：PCT/GB2004/001613

申请日：2004-04-15

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  IBM UNITED KINGDOM LIMITED ,  KALLA, Ronald ,  PHAM, Minh, Michelle ,  WARD III, John

Inventor： KALLA, Ronald ,  PHAM, Minh, Michelle ,  WARD III, John

IPC: G06F1/32

CPC classification number: G06F9/3836 ,  G06F9/30189 ,  G06F9/3851 ,  G06F9/3869

Abstract: A register in the control unit of the CPU that is used to keep track of the address of the current or next instruction is called a program counter. In an SMT system having two threads, the CPU has program counters for both threads and means for alternately selecting between program counters to determine which thread supplies an instruction to the instruction fetch unit (IFU). The software for the SMT assigns a priority to threads entering the code stream. Instructions from the threads are read from the instruction queues pseudo-randomly and proportional to their execution priorities in the normal power mode. If both threads have a lowest priority, a low power mode is set generating a gated select time every N clock cycles of a clock when valid instructions are loaded. N may be adjusted to vary the amount of power savings and the gated select time.

公开(公告)号：WO2004095282A1

公开(公告)日：2004-11-04

申请号：PCT/GB2004/001586

申请日：2004-04-14

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  IBM UNITED KINGDOM LIMITED ,  ARMSTRONG, William, Joseph ,  FLOYD, Michael, Stephen ,  LEITNER, Larry, Scott ,  KALLA, Ronald, Nick ,  SINHAROY, Balaram

Inventor： ARMSTRONG, William, Joseph ,  FLOYD, Michael, Stephen ,  LEITNER, Larry, Scott ,  KALLA, Ronald, Nick ,  SINHAROY, Balaram

IPC: G06F11/34

CPC classification number: G06F9/3851 ,  G06F9/50 ,  G06F11/3419 ,  G06F11/348 ,  G06F2201/88 ,  G06F2201/885

Abstract: An accounting method and logic for determining per-thread processor resource utilization in a simultaneous multi-threaded (SMT) processor provides a mechanism for accounting for processor resource usage by programs and threads within programs. Relative resource use is determined by detecting instruction dispatches for multiple threads active within the processor, which may include idle threads that are still occupying processor resources. If instructions are dispatched for all threads or no threads, the processor cycle is accounted equally to all threads. Alternatively if no threads are in a dispatch state, the accounting may be made using a prior state, or in conformity with ratios of the threads' priority levels. If only one thread is dispatching, that thread is accounted the entire processor cycle. If multiple threads are dispatching, but less than all threads are dispatching (in processors supporting more than two threads), the processor cycle is billed evenly across the dispatching threads. Multiple dispatches may be detected for the threads and a fractional resource usage determined for each thread and the counters may be updated in accordance with their fractional usage.

Abstract translation: 用于确定同时多线程（SMT）处理器中的每线程处理器资源利用的计费方法和逻辑提供了一种用于计算程序内的程序和线程的处理器资源使用的机制。 通过检测处理器内活动的多个线程的指令分派来确定相对资源使用，这可能包括仍占用处理器资源的空闲线程。 如果为所有线程或没有线程调度指令，则处理器周期与所有线程相等。 或者，如果没有线程处于调度状态，则可以使用先前状态进行计费，或者根据线程的优先级的比率来进行计费。 如果只调度一个线程，则该线程将占整个处理器周期。 如果多个线程正在调度，但是少于所有线程的调度（在支持多于两个线程的处理器中），处理器周期将在调度线程之间平均计费。 可以为线程检测多个调度，并且为每个线程确定的分数资源使用，并且可以根据其分数使用来更新计数器。

公开(公告)号：WO2004095245A3

公开(公告)日：2005-04-21

申请号：PCT/GB2004001613

申请日：2004-04-15

Applicant: IBM ,  IBM UK ,  KALLA RONALD ,  PHAM MINH MICHELLE ,  WARD III JOHN

Inventor： KALLA RONALD ,  PHAM MINH MICHELLE ,  WARD III JOHN

IPC: G06F1/26 ,  G06F1/32 ,  G06F9/318 ,  G06F9/38

CPC classification number: G06F9/3836 ,  G06F9/30189 ,  G06F9/3851 ,  G06F9/3869

Abstract: A register in the control unit of the CPU that is used to keep track of the address of the current or next instruction is called a program counter. In an SMT system having two threads, the CPU has program counters for both threads and means for alternately selecting between program counters to determine which thread supplies an instruction to the instruction fetch unit (IFU). The software for the SMT assigns a priority to threads entering the code stream. Instructions from the threads are read from the instruction queues pseudo-randomly and proportional to their execution priorities in the normal power mode. If both threads have a lowest priority, a low power mode is set generating a gated select time every N clock cycles of a clock when valid instructions are loaded. N may be adjusted to vary the amount of power savings and the gated select time.

Abstract translation: 用于跟踪当前或下一条指令的地址的CPU的控制单元中的寄存器称为程序计数器。 在具有两个线程的SMT系统中，CPU具有用于两个线程的程序计数器和用于在程序计数器之间交替选择以确定哪个线程向指令获取单元（IFU）提供指令的装置。 用于SMT的软件为输入代码流的线程分配优先级。 来自线程的指令从指令队列中伪随机地读取，并与其在正常功率模式下的执行优先级成比例。 如果两个线程具有最低优先级，则设置低功率模式，当加载有效指令时，每N个时钟周期产生门控选择时间。 可以调节N以改变功率节省量和选通时间。