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    PROGRAMMABLE VARIABLE LENGTH DECODER INCLUDING INTERFACE OF CPU PROCESSOR
    2.
    发明申请
    PROGRAMMABLE VARIABLE LENGTH DECODER INCLUDING INTERFACE OF CPU PROCESSOR 审中-公开
    可编程长度解码器，包括CPU处理器接口

    公开(公告)号：WO2003098809A1

    公开(公告)日：2003-11-27

    申请号：PCT/KR2003/000970

    申请日：2003-05-16

    Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE ,  KOO, Bon-Tae ,  KIM, Ig-Kyun

    Inventor： KOO, Bon-Tae ,  KIM, Ig-Kyun

    IPC: H03M7/40

    CPC classification number: H03M7/42

    Abstract: Provided is a programmable variable-length decoder that interfaces with an external processor. The programmable variable-length decoder includes a memory buffer, a latching unit, a multiplexing unit, a first barrel shifter, a decoding unit, and a control unit. The memory buffer stores input serial bit stream data for decoding in fixed-length data segments and outputs the stored bit stream data in response to a first control signal. The latching unit temporarily stores data output from the memory buffer and outputs the stored data in response to the first control signal. The multiplexing unit selects data from the latching unit and outputs the selected data. The first barrel shifter shifts the output of the multiplexing unit by the value of a second control signal and outputs the shifted data. The decoding unit decodes the output of the first barrel shifter and outputs decoded codewords and is the bit length of the decoded codewords. The control unit adds together the bit lengths of currently decoded codewords and the bit lengths of previously decoded codewords, stores the sum, generates the first control signal and the second control signal based on the sum, and outputs the first control signal and the second control signal to the latching unit and the first barrel shifter.

    Abstract translation: 提供与外部处理器接口的可编程可变长度解码器。 可编程可变长度解码器包括存储器缓冲器，锁存单元，复用单元，第一桶形移位器，解码单元和控制单元。 存储器缓冲器存储用于在固定长度数据段中解码的输入串行比特流数据，并且响应于第一控制信号输出存储的比特流数据。 锁存单元临时存储从存储器缓冲器输出的数据，并响应于第一控制信号输出存储的数据。 复用单元从锁存单元中选择数据并输出所选择的数据。 第一桶形移位器将复用单元的输出移位第二控制信号的值，并输出移位数据。 解码单元解码第一桶形移位器的输出并输出解码码字，并且是解码码字的位长度。 控制单元将当前解码的码字的比特长度和先前解码的码字的比特长度相加在一起，存储该和，基于该和产生第一控制信号和第二控制信号，并输出第一控制信号和第二控制 信号到锁存单元和第一桶形移位器。

    ADDRESS GENERATOR FOR SEARCHING ALGEBRAIC CODEBOOK
    4.
    发明申请
    ADDRESS GENERATOR FOR SEARCHING ALGEBRAIC CODEBOOK 审中-公开
    寻址代码代码的地址发生器

    公开(公告)号：US20100153100A1

    公开(公告)日：2010-06-17

    申请号：US12553736

    申请日：2009-09-03

    Applicant: Byun Kyung Jin ,  Koo Bon Tae ,  Eum Nak Woong

    Inventor： Byun Kyung Jin ,  Koo Bon Tae ,  Eum Nak Woong

    IPC: G10L19/00

    CPC classification number: G10L19/107 ,  G10L2019/0008 ,  G10L2019/0013

    Abstract: An address generator for searching an algebraic codebook is disclosed. The address generator includes: a multiplier multiplying the dimension and a width value of a correlation matrix; a first adder adding a length value and an offset address of the correlation matrix; and a second adder adding the results of the multiplier and the first adder to generate an address for algebraic codebook searching. The amount of calculation required for an address calculation to search an algebraic codebook can be reduced.

    Abstract translation: 公开了一种用于搜索代数码本的地址发生器。 地址生成器包括：乘法器，乘以相关矩阵的维度和宽度值; 第一加法器，相加矩阵的长度值和偏移地址; 以及将乘法器和第一加法器的结果相加以生成代数码本搜索的地址的第二加法器。 可以减少地址计算所需的搜索代数码本所需的计算量。

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