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    SEMI-CONDUCTOR COMPONENT AS A DELAYING DEVICE AND USE THEREOF.
    1.
    发明申请
    SEMI-CONDUCTOR COMPONENT AS A DELAYING DEVICE AND USE THEREOF. 审中-公开
    半导体部件时延元件及半导体元件的使用

    公开(公告)号：WO0117025A2

    公开(公告)日：2001-03-08

    申请号：PCT/DE0003002

    申请日：2000-09-01

    Applicant: INFINEON TECHNOLOGIES AG ,  BRUECKLMEIER ERIC ROGER ,  PALM HERBERT ,  KUX ANDREAS

    Inventor： BRUECKLMEIER ERIC-ROGER ,  PALM HERBERT ,  KUX ANDREAS

    IPC: H01L29/423 ,  H01L29/788 ,  H01L29/00

    CPC classification number: H01L29/7883 ,  H01L29/42328

    Abstract: A floating gate cell is used as a clock whereby the charging process is delayed by the application of a sufficiently low charging voltage until a predetermined threshold voltage is reached. A particularly thin tunnel oxide layer can be provided in order to bring about a gradual discharge of a charged cell. Preferably, the floating gate electrode (5)is connected to the control gate electrode (16) of a second cell, which then delays the charging of the floating gate electrode (15) of the second cell.

    Abstract translation: 通过在充电过程的时间尺度被延迟，直到通过施加足够低的充电电压的预定阈值电压被使用的浮动栅极单元。 特别薄的隧道可旨在实现加载细胞的逐渐放电。 优选地，浮置栅极电极（5）到所述控制栅电极（16）连接到第二小区，其然后相应地降低时，浮置栅电极（15）加载所述第二小区。

    CHIPCARD ARRANGEMENT
    2.
    发明申请
    CHIPCARD ARRANGEMENT 审中-公开
    SMART CARD ASSEMBLY

    公开(公告)号：WO0152184A3

    公开(公告)日：2002-02-07

    申请号：PCT/DE0004634

    申请日：2000-12-27

    Applicant: INFINEON TECHNOLOGIES AG ,  KUX ANDREAS

    Inventor： KUX ANDREAS

    IPC: G06K19/00 ,  G06K19/073 ,  G06K19/077 ,  H01L25/065

    CPC classification number: G06K19/072 ,  G06K19/07372 ,  G06K19/077 ,  H01L25/0657 ,  H01L2225/06513 ,  H01L2225/06582 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: The invention relates to a chipcard arrangement with a card-like support, in which a recess is provided, with at least two superimposed semiconductor chips (4, 5) arranged therein. Said chips exchange electrical signals and/or energy, with each other, by means of electrically conducting connectors, whereby the at least two semiconductor chips (4, 5) together have a minimum size of from 20 to 25 mm and the electrically conducting connection is achieved by means of a three-dimensional wiring in the semiconductor chip.

    Abstract translation: 与卡形载体的芯片卡装置，其中被设置的凹部，被布置在至少两个叠置的半导体芯片（4,5），其经由导电连接的电信号和/或能量，彼此交换，其中所述至少两个半导体芯片（4,5 ）一起具有20〜25毫米的最小尺寸和导电连接是通过在半导体芯片的三维布线来实现。

    METHOD FOR MARKING A SOLAR CELL, AND SOLAR CELL
    3.
    发明申请
    METHOD FOR MARKING A SOLAR CELL, AND SOLAR CELL 审中-公开
    标记太阳能电池的方法和太阳能电池

    公开(公告)号：WO2012013214A3

    公开(公告)日：2012-05-31

    申请号：PCT/EP2010060790

    申请日：2010-07-26

    Applicant: CELLS SE Q ,  HLUSIAK MARKUS ,  SWIATKOWSKI CARSTEN ,  SCHERFF MAXIMILIAN ,  MUELLER JOERG ,  KUX ANDREAS

    Inventor： HLUSIAK MARKUS ,  SWIATKOWSKI CARSTEN ,  SCHERFF MAXIMILIAN ,  MUELLER JOERG ,  KUX ANDREAS

    IPC: H01L31/02 ,  H01L23/544 ,  H01L31/0236

    CPC classification number: H01L31/0236 ,  H01L23/544 ,  H01L31/18 ,  H01L2223/54406 ,  H01L2223/54413 ,  H01L2223/54433 ,  H01L2223/54493 ,  H01L2924/0002 ,  Y02E10/50 ,  H01L2924/00

    Abstract: The invention relates to a method for marking a solar cell, comprising the following steps: Providing a solar cell substrate (1 ); Selecting an identification pattern for identifying the solar cell substrate (1 ) during process steps of a manufacturing process for the solar cell and / or for tracing back the solar cell substrate (1 ) after assembly of the solar cell in a solar cell module; Forming an etch resist layer (3) on a surface (2) of the solar cell substrate (1 ); Etching the surface (2) of the solar cell substrate (1 ) with an etchant, whereby the etch resist layer (3) is formed in such a way that a pattern region (4) of the surface (2) in the shape of the identification pattern is protected from the etchant. Furthermore, the invention relates to a solar cell.

    Abstract translation: 本发明涉及一种用于标记太阳能电池的方法，包括以下步骤：提供太阳能电池基板（1）; 在太阳能电池模块中组装太阳能电池之后，选择用于在太阳能电池的制造过程的处理步骤期间和/或追溯太阳能电池基板（1）的用于识别太阳能电池基板（1）的识别模式; 在太阳能电池基板（1）的表面（2）上形成抗蚀剂层（3）; 用蚀刻剂蚀刻太阳能电池基板（1）的表面（2），由此形成蚀刻保护层（3），使得表面（2）的图案区域（4） 识别图案被保护而不受蚀刻剂影响。 此外，本发明涉及太阳能电池。

    METHOD FOR MARKING A SOLAR CELL, AND SOLAR CELL
    4.
    发明申请
    METHOD FOR MARKING A SOLAR CELL, AND SOLAR CELL 审中-公开
    用于标记太阳能电池和太阳能电池的方法

    公开(公告)号：WO2012013214A2

    公开(公告)日：2012-02-02

    申请号：PCT/EP2010/060790

    申请日：2010-07-26

    Applicant: Q-CELLS SE ,  HLUSIAK, Markus ,  SWIATKOWSKI, Carsten ,  SCHERFF, Maximilian ,  MÜLLER, Jörg ,  KUX, Andreas

    Inventor： HLUSIAK, Markus ,  SWIATKOWSKI, Carsten ,  SCHERFF, Maximilian ,  MÜLLER, Jörg ,  KUX, Andreas

    IPC: H01L31/18

    CPC classification number: H01L31/0236 ,  H01L23/544 ,  H01L31/18 ,  H01L2223/54406 ,  H01L2223/54413 ,  H01L2223/54433 ,  H01L2223/54493 ,  H01L2924/0002 ,  Y02E10/50 ,  H01L2924/00

    Abstract: The invention relates to a method for marking a solar cell, comprising the following steps: Providing a solar cell substrate (1 ); Selecting an identification pattern for identifying the solar cell substrate (1 ) during process steps of a manufacturing process for the solar cell and / or for tracing back the solar cell substrate (1 ) after assembly of the solar cell in a solar cell module; Forming an etch resist layer (3) on a surface (2) of the solar cell substrate (1 ); Etching the surface (2) of the solar cell substrate (1 ) with an etchant, whereby the etch resist layer (3) is formed in such a way that a pattern region (4) of the surface (2) in the shape of the identification pattern is protected from the etchant. Furthermore, the invention relates to a solar cell.

    Abstract translation: 本发明涉及一种用于标记太阳能电池的方法，包括以下步骤：提供太阳能电池基板（1）; 在太阳能电池组件中组装太阳能电池之后，选择在太阳能电池制造过程的工艺步骤和/或跟踪太阳能电池基板（1）期间识别太阳能电池基板（1）的识别图案; 在太阳能电池基板（1）的表面（2）上形成蚀刻抗蚀剂层（3）。 用蚀刻剂蚀刻太阳能电池基板（1）的表面（2），由此形成蚀刻抗蚀剂层（3），使得表面（2）的图案区域（4）形状为 识别图案受到蚀刻剂的保护。 此外，本发明涉及一种太阳能电池。

    METHOD FOR MARKING A SOLAR CELL AND SOLAR CELL
    5.
    发明申请
    METHOD FOR MARKING A SOLAR CELL AND SOLAR CELL 审中-公开
    用于标记太阳能电池和太阳能电池的方法

    公开(公告)号：WO2011154033A2

    公开(公告)日：2011-12-15

    申请号：PCT/EP2010/057939

    申请日：2010-06-07

    Applicant: Q-CELLS SE ,  MÜLLER, Jörg ,  SCHERFF, Maximilian ,  HLUSIAK, Markus ,  SWIATKOWSKI, Carsten ,  KUX, Andreas

    Inventor： MÜLLER, Jörg ,  SCHERFF, Maximilian ,  HLUSIAK, Markus ,  SWIATKOWSKI, Carsten ,  KUX, Andreas

    IPC: H01L31/02

    CPC classification number: H01L31/02 ,  H01L23/544 ,  H01L31/02245 ,  H01L31/022458 ,  H01L2223/54413 ,  H01L2223/54433 ,  H01L2223/54473 ,  H01L2924/0002 ,  Y02E10/50 ,  H01L2924/00

    Abstract: The invention relates to a method for marking a solar cell, the method comprising the following steps: providing the solar cell substrate (1); selecting an identification mark (7) for identifying the solar cell substrate (1) during process steps of a manufacturing process for the solar cell; and forming a multitude of through-holes (2) through the substrate, whereby at least a fraction of the multitude of through-holes (2) is intended as emitter wrap through or metal wrap through holes for the solar cell, such that the identification mark is represented by a geometrical property of one or more marking through-holes (21) selected from the multitude of through-holes (2), as well as a solar cell.

    Abstract translation: 本发明涉及一种用于标记太阳能电池的方法，该方法包括以下步骤：提供太阳能电池基板（1）; 在太阳能电池的制造过程的处理步骤期间选择用于识别太阳能电池基板（1）的识别标记（7） 以及通过所述基板形成多个通孔（2），由此所述多个通孔（2）的至少一部分用作所述太阳能电池的发射器包裹通孔或金属包裹通孔，使得所述识别 标记由选自多个通孔（2）中的一个或多个标记通孔（21）的几何特性以及太阳能电池表示。

    CIRCUIT
    7.
    发明申请
    CIRCUIT 审中-公开
    电路

    公开(公告)号：WO02054492A3

    公开(公告)日：2003-02-13

    申请号：PCT/DE0104589

    申请日：2001-12-06

    Applicant: INFINEON TECHNOLOGIES AG ,  KUX ANDREAS

    Inventor： KUX ANDREAS

    IPC: H01L23/544 ,  H01L23/58 ,  H01L29/06

    CPC classification number: H01L23/57 ,  H01L23/544 ,  H01L24/31 ,  H01L29/0657 ,  H01L2223/54473 ,  H01L2924/01068 ,  H01L2924/10158 ,  H01L2924/14 ,  H01L2924/19041

    Abstract: The invention relates to a circuit comprising a first substrate (1) which has an integrated circuit (4) in a first surface (3) and a second surface (2) opposite the same, and a second substrate (9) which has a sensor (7) on one surface. Said second substrate (9) is adhesively connected to the first substrate (1) in such a way that the surface of the second substrate (9) comprising the sensor (7) faces one of the two surfaces (2, 3) of the first substrate (1). It can thus be determined whether the arrangement consisting of the first and second substrate is divided or has been divided.

    Abstract translation: 具有第一衬底的电路布置（1），在第一表面（3）的集成电路（4）和相对的第二面（2）和MT的第二基板（9），使得传感器的表面（7）上 ，其中所述第二衬底（9）连接到第一基板（1）是这样附着第二基板的表面（9），其具有传感器（7），所述两个表面中的一个（2,3）的第一的 基板（1）面对。 因此，被检测的第一和第二衬底的排列是否被分离，或者在。

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