公开(公告)号：US08936983B2

公开(公告)日：2015-01-20

申请号：US13325312

申请日：2011-12-14

Applicant: Kang Jae Lee ,  Eun Joo Jung

Inventor： Kang Jae Lee ,  Eun Joo Jung

IPC: H01L21/336 ,  H01L27/115

CPC classification number: H01L27/11534 ,  H01L27/11529

Abstract: A method of fabricating a semiconductor device according to present invention includes forming a stack layers on a semiconductor substrate having a first area and a second area; forming first gates on the semiconductor substrate of the first area by patterning the stack layers, wherein the first gates are formed a first distance apart from each other; forming a first impurity injection area in the semiconductor substrate of the first area exposed at both sides of each of the first gates; filling a space between the first gates with an insulating layer; forming second gates on the semiconductor substrate of the second area by patterning the stack layers, wherein the second gates are formed a second distance apart from each other, and wherein the second distance is larger than the first distance; and forming a second impurity injection area in the semiconductor device of the second area exposed between the second gates.

Abstract translation: 根据本发明的制造半导体器件的方法包括在具有第一区域和第二区域的半导体衬底上形成堆叠层; 通过图案化所述堆叠层，在所述第一区域的所述半导体衬底上形成第一栅极，其中所述第一栅极彼此分开形成第一距离; 在所述第一栅极的两侧露出的所述第一区域的半导体衬底中形成第一杂质注入区域; 用绝缘层填充第一栅极之间的空间; 通过对所述堆叠层进行构图来形成所述第二区域的所述半导体衬底上的第二栅极，其中所述第二栅极彼此分开形成第二距离，并且其中所述第二距离大于所述第一距离; 以及在所述第二栅极之间暴露的所述第二区域的所述半导体器件中形成第二杂质注入区域。

公开(公告)号：US20120156841A1

公开(公告)日：2012-06-21

申请号：US13325312

申请日：2011-12-14

Applicant: Kang Jae LEE ,  Eun Joo JUNG

Inventor： Kang Jae LEE ,  Eun Joo JUNG

IPC: H01L21/336

CPC classification number: H01L27/11534 ,  H01L27/11529

Abstract: A method of fabricating a semiconductor device according to present invention includes forming a stack layers on a semiconductor substrate having a first area and a second area; forming first gates on the semiconductor substrate of the first area by patterning the stack layers, wherein the first gates are formed a first distance apart from each other; forming a first impurity injection area in the semiconductor substrate of the first area exposed at both sides of each of the first gates; filling a space between the first gates with an insulating layer; forming second gates on the semiconductor substrate of the second area by patterning the stack layers, wherein the second gates are formed a second distance apart from each other, and wherein the second distance is larger than the first distance; and forming a second impurity injection area in the semiconductor device of the second area exposed between the second gates.

Abstract translation: 根据本发明的制造半导体器件的方法包括在具有第一区域和第二区域的半导体衬底上形成堆叠层; 通过图案化所述堆叠层，在所述第一区域的所述半导体衬底上形成第一栅极，其中所述第一栅极彼此分开形成第一距离; 在所述第一栅极的两侧露出的所述第一区域的半导体衬底中形成第一杂质注入区域; 用绝缘层填充第一栅极之间的空间; 通过对所述堆叠层进行构图来形成所述第二区域的所述半导体衬底上的第二栅极，其中所述第二栅极彼此分开形成第二距离，并且其中所述第二距离大于所述第一距离; 以及在所述第二栅极之间暴露的所述第二区域的所述半导体器件中形成第二杂质注入区域。

公开(公告)号：US20110147823A1

公开(公告)日：2011-06-23

申请号：US12964233

申请日：2010-12-09

Applicant: Seoung-Woo KUK ,  Kang-Jae Lee

Inventor： Seoung-Woo KUK ,  Kang-Jae Lee

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L27/11551 ,  H01L27/11556 ,  H01L27/11578

Abstract: A method for fabricating a vertical channel type nonvolatile memory device includes forming alternately a plurality of interlayer dielectric layers and a plurality of conductive layers over a substrate, forming a trench having a plurality of recesses on a surface of the trench by etching the plurality of interlayer dielectric layers and a plurality of conductive layers, wherein the plurality of recesses are formed at a certain interval on the surface of the trench, forming a charge blocking layer over a plurality of surfaces of the plurality of recesses, forming a charge storage layer over the charge blocking layer for filling a plurality of the remaining recesses with a charge storage material, forming a tunnel dielectric layer to cover the charge storage layer, and forming a vertical channel layer by filling the remaining trench.

Abstract translation: 一种用于制造垂直沟道型非易失性存储器件的方法包括在衬底上交替地形成多个层间电介质层和多个导电层，通过蚀刻多个中间层在沟槽的表面上形成具有多个凹槽的沟槽 电介质层和多个导电层，其中所述多个凹槽在所述沟槽的表面上以一定间隔形成，在所述多个凹槽的多个表面上形成电荷阻挡层，在所述多个凹槽的上方形成电荷存储层 电荷阻挡层，用于用电荷存储材料填充多个剩余的凹槽，形成隧道电介质层以覆盖电荷存储层，以及通过填充剩余的沟槽形成垂直沟道层。

公开(公告)号：US08519471B2

公开(公告)日：2013-08-27

申请号：US12964233

申请日：2010-12-09

Applicant: Seoung-Woo Kuk ,  Kang-Jae Lee

Inventor： Seoung-Woo Kuk ,  Kang-Jae Lee

IPC: H01L29/792

CPC classification number: H01L27/11551 ,  H01L27/11556 ,  H01L27/11578

Abstract: A method for fabricating a vertical channel type nonvolatile memory device includes forming alternately a plurality of interlayer dielectric layers and a plurality of conductive layers over a substrate, forming a trench having a plurality of recesses on a surface of the trench by etching the plurality of interlayer dielectric layers and a plurality of conductive layers, wherein the plurality of recesses are formed at a certain interval on the surface of the trench, forming a charge blocking layer over a plurality of surfaces of the plurality of recesses, forming a charge storage layer over the charge blocking layer for filling a plurality of the remaining recesses with a charge storage material, forming a tunnel dielectric layer to cover the charge storage layer, and forming a vertical channel layer by filling the remaining trench.

Abstract translation: 一种用于制造垂直沟道型非易失性存储器件的方法包括在衬底上交替地形成多个层间电介质层和多个导电层，通过蚀刻多个中间层在沟槽的表面上形成具有多个凹槽的沟槽 电介质层和多个导电层，其中所述多个凹槽在所述沟槽的表面上以一定间隔形成，在所述多个凹槽的多个表面上形成电荷阻挡层，在所述多个凹槽的上方形成电荷存储层 电荷阻挡层，用于用电荷存储材料填充多个剩余的凹槽，形成隧道电介质层以覆盖电荷存储层，以及通过填充剩余的沟槽形成垂直沟道层。