Abstract:
An adjusting apparatus has a barrel 20 with a closed end 21, a neck portion 22 on the closed end and bores 24 on the closed end. An adjusting assembly 30 with an outer tube 31 and an inner tube 32 is connected to the neck portion of the barrel. A driving member 50, which is received in the barrel 20, has posts inserted into the bores of the barrel respectively and extruded out of the barrel to be rested on the adjusting assembly. A washer assembly 60 has a bearing 62 which is received in the barrel behind the driving member A movable member 70 has a gear portion 71 and two blocks 72 to be received in the barrel. A transmission shaft 80 has an annular gear portion 82 to be inserted into the barrel via the neck portion and the gear portion of the transmission shaft is meshed with the gear portion of the movable member. A spring 90 is received in the barrel behind the washer assembly to urge the driving member outwards.
Abstract:
A spring (90) is provided behind a drive component (50) and a disk structure (60) within a drum (20) and biases both drive component and disk structure forward. The movable element (70) within the disk structure is moved away from the drive block (3) of a transmission hub (1) within the drum. The drive component has posts (51) penetrated through the openings (24) around the neck (22) of the drum. The posts engage into a torque adjustment mechanism (30). A transmission shaft (80) penetrates into the drum and engages with the off-cut (71) formed to the movable element.
Abstract:
Graphene-channel based devices and techniques for the fabrication thereof are provided. In one aspect, a semiconductor device includes a first wafer having at least one graphene channel formed on a first substrate, a first oxide layer surrounding the graphene channel and source and drain contacts to the graphene channel that extend through the first oxide layer; and a second wafer having a CMOS device layer formed in a second substrate, a second oxide layer surrounding the CMOS device layer and a plurality of contacts to the CMOS device layer that extend through the second oxide layer, the wafers being bonded together by way of an oxide-to-oxide bond between the oxide layers. One or more of the contacts to the CMOS device layer are in contact with the source and drain contacts. One or more other of the contacts to the CMOS device layer are gate contacts for the graphene channel.
Abstract:
Graphene- and/or carbon nanotube-based radiation-hard transistor devices and techniques for the fabrication thereof are provided. In one aspect, a method of fabricating a radiation-hard transistor is provided. The method includes the following steps. A radiation-hard substrate is provided. A carbon-based material is formed on the substrate wherein a portion of the carbon-based material serves as a channel region of the transistor and other portions of the carbon-based material serve as source and drain regions of the transistor. Contacts are formed to the portions of the carbon-based material that serve as the source and drain regions of the transistor. A gate dielectric is deposited over the portion of the carbon-based material that serves as the channel region of the transistor. A top-gate contact is formed on the gate dielectric.
Abstract:
A graphene-based field effect transistor includes source and drain electrodes that are self-aligned to a gate electrode. A stack of a seed layer and a dielectric metal oxide layer is deposited over a patterned graphene layer. A conductive material stack of a first metal portion and a second metal portion is formed above the dielectric metal oxide layer. The first metal portion is laterally etched employing the second metal portion, and exposed portions of the dielectric metal oxide layer are removed to form a gate structure in which the second metal portion overhangs the first metal portion. The seed layer is removed and the overhang is employed to shadow proximal regions around the gate structure during a directional deposition process to form source and drain electrodes that are self-aligned and minimally laterally spaced from edges of the gate electrode.
Abstract:
Techniques for fabricating carbon nanotube-based devices are provided. In one aspect, a method for fabricating a carbon nanotube-based integrated circuit is provided. The method comprises the following steps. A first wafer comprising carbon nanotubes is provided. A second wafer comprising one or more device elements is provided. One or more of the carbon nanotubes are connected with one or more of the device elements by bonding the first wafer and the second wafer together. A carbon nanotube-based integrated circuit is also provided.
Abstract:
A photodetector which uses single or multi-layer graphene as the photon detecting layer is disclosed. Multiple embodiments are disclosed with different configurations of electrodes. In addition, a photodetector array comprising multiple photodetecting elements is disclosed for applications such as imaging and monitoring.
Abstract:
A graphene field effect transistor includes a gate stack, the gate stack including a seed layer, a gate oxide formed over the seed layer, and a gate metal formed over the gate oxide; an insulating layer; and a graphene sheet displaced between the seed layer and the insulating layer.
Abstract:
A photodetector which uses single or multi-layer graphene on a gate oxide layer (12) as the photon detecting layer (14) is disclosed. Multiple embodiments are disclosed with different configurations of the source (8), drain (6) and gate (10) electrodes. In addition, a photodetector array comprising multiple photodetecting elements is disclosed for applications such as imaging and monitoring. An optical waveguide underlying the graphene layer (14) may be embedded into substrate (10) or gate oxide layer (12) in order to channel photons towards graphene layer (14).