公开(公告)号：WO2004003967A3

公开(公告)日：2009-06-18

申请号：PCT/US0315434

申请日：2003-05-16

Applicant: LOGICVISION CANADA INC ,  COTE JEAN-FRANCOIS ,  NADEAU-DOSTIE BENOIT

Inventor： COTE JEAN-FRANCOIS ,  NADEAU-DOSTIE BENOIT

IPC: G01R31/28 ,  G01R31/3185

CPC classification number: G01R31/318563 ,  G01R31/318555 ,  G01R31/318566 ,  G06F2201/83

Abstract: A method of scan testing an integrated circuit to provide real time identification of a block of test patterns having at least one failing test pattern comprises performing (120) a number of test operations and storing (122) a test response signature corresponding to each block of test patterns into a signature register; replacing (124) the test response signature in the signature register with a test block expected signature; identifying (126) the block as a failing test block (128) when the test response signature is different from the test block expected signature; and repeating preceding steps until the test is complete.

Abstract translation: 一种扫描测试集成电路以提供具有至少一个故障测试图案的测试图案块的实时识别的方法包括执行（120）多个测试操作并存储（122）与每个块的测试响应签名相对应的测试响应签名 测试模式进入签名寄存器; 在签名寄存器中用测试块预期签名代替（124）测试响应签名; 当所述测试响应签名与所述测试块预期签名不同时，将所述块识别（126）为失败测试块（128）; 并重复前面的步骤，直到测试完成。

公开(公告)号：WO2004025698A3

公开(公告)日：2004-08-05

申请号：PCT/US0324699

申请日：2003-08-08

Applicant: LOGICVISION CANADA INC ,  SUNTER STEPHEN K

Inventor： SUNTER STEPHEN K

IPC: G01R31/28 ,  G01R1/04

CPC classification number: G01R31/2841 ,  G01R31/2886

Abstract: A method for accurately delivering a voltage to a circuit node of an integrated circuit having analog buses and transmission gates selectively connecting the circuit node to the buses, comprises sensing the voltage on the circuit node via a first of the buses under control of a first periodic signal; applying a first stimulus voltage to the circuit node via a second bus under control of a second periodic signal; and applying a second stimulus voltage to the circuit node under control of a third periodic signal which is inverted with respect to the second periodic signal so that the circuit node is driven alternately to the first stimulus voltage and to the second stimulus voltage.

Abstract translation: 一种用于将电压精确地传送到具有选择性地将电路节点连接到总线的模拟总线和传输门的集成电路的电路节点的方法包括在第一周期的控制下经由第一总线检测电路节点上的电压 信号; 在第二周期信号的控制下经由第二总线在电路节点上施加第一刺激电压; 以及在相对于所述第二周期信号反相的第三周期信号的控制下，向所述电路节点施加第二刺激电压，使得所述电路节点被交替驱动到所述第一刺激电压和所述第二刺激电压。

公开(公告)号：AU2003205269A1

公开(公告)日：2003-09-02

申请号：AU2003205269

申请日：2003-01-23

Applicant: LOGICVISION CANADA INC

Inventor： PAJAK BRIAN JOHN ,  PRICE PAUL ,  ROMAIN LUC ,  COTE JEAN-FRANCOIS

IPC: G01R31/317 ,  G01R31/3183 ,  G01R31/3185 ,  G06F17/50 ,  G01R31/14

公开(公告)号：AU2003297666A8

公开(公告)日：2004-07-29

申请号：AU2003297666

申请日：2003-12-05

Applicant: LOGICVISION CANADA INC

Inventor： SUNTER STEPHEN K ,  ROY AUBIN P J

IPC: G01R31/28 ,  G01R31/317 ,  G01R31/3185 ,  G01R31/02

Abstract: A circuit and method are described in which a DC voltage or current is connected to a high frequency, AC-coupled signal path between a transmitter and a receiver, and the bit error rate of the data transmission is tested while applying an altered bias voltage to the received signal. The bias voltage can be connected via a resistor, inductor or transistors. The transmitted signal is attenuated resistively, and a load capacitance is applied whose value causes digital transition times to exceed one unit interval. An intended application is testing of an integrated circuit, serializer/deserializer (serdes) operating above 1 GHz.

公开(公告)号：AU2003258135A8

公开(公告)日：2004-04-30

申请号：AU2003258135

申请日：2003-08-08

Applicant: SUNTER STEPHEN K ,  LOGICVISION CANADA INC

Inventor： SUNTER STEPHEN K

IPC: G01R31/28 ,  G01R1/04

Abstract: A method for accurately delivering a voltage to a circuit node of an integrated circuit having analog buses and transmission gates selectively connecting the circuit node to the buses, comprises sensing the voltage on the circuit node via a first of the buses under control of a first periodic signal; applying a first stimulus voltage to the circuit node via a second bus under control of a second periodic signal; and applying a second stimulus voltage to the circuit node under control of a third periodic signal which is inverted with respect to the second periodic signal so that the circuit node is driven alternately to the first stimulus voltage and to the second stimulus voltage.

公开(公告)号：WO2004061459A3

公开(公告)日：2004-12-23

申请号：PCT/US0338648

申请日：2003-12-05

Applicant: LOGICVISION CANADA INC ,  SUNTER STEPHEN K ,  ROY AUBIN P J

Inventor： SUNTER STEPHEN K ,  ROY AUBIN P J

IPC: G01R31/28 ,  G01R31/317 ,  G01R31/3185 ,  G01R31/02

CPC classification number: G01R31/2834 ,  G01R31/2884 ,  G01R31/3171 ,  G01R31/31725 ,  G01R31/318577 ,  G01R31/31858 ,  G01R31/318594

Abstract: A circuit and method are described in which a DC voltage or current is connected to a high frequency, AC-coupled signal path between a transmitter and a receiver, and the bit error rate of the data transmission is tested while applying an altered bias voltage to the received signal. The bias voltage can be connected via a resistor, inductor or transistors. The transmitted signal is attenuated resistively, and a load capacitance is applied whose value causes digital transition times to exceed one unit interval. An intended application is testing of an integrated circuit, serializer/deserializer (serdes) operating above 1 GHz.

Abstract translation: 描述了一种电路和方法，其中直流电压或电流连接到发射机和接收机之间的高频交流耦合信号路径，并且在施加改变的偏置电压的同时测试数据传输的误码率 接收信号。 偏置电压可以通过电阻，电感或晶体管连接。 发送的信号被电阻衰减，并且施加负载电容，其值导致数字转换时间超过一个单位间隔。 预期的应用是测试在1 GHz以上运行的集成电路，串行器/解串器（Serdes）。

公开(公告)号：AU2003234616A8

公开(公告)日：2009-07-30

申请号：AU2003234616

申请日：2003-05-16

Applicant: LOGICVISION CANADA INC

Inventor： NADEAU-DOSTIE BENOIT ,  COTE JEAN-FRANCOIS

IPC: G01R31/28 ,  G01R31/3185

Abstract: A method of scan testing an integrated circuit to provide real time identification of a block of test patterns having at least one failing test pattern comprises performing a number of test operations and storing a test response signature corresponding to each block of test patterns into a signature register; replacing the test response signature in the signature register with a test block expected signature; identifying the block as a failing test block when the test response signature is different from the test block expected signature; and repeating preceding steps until the test is complete.