公开(公告)号：WO2008152026A4

公开(公告)日：2009-04-09

申请号：PCT/EP2008057196

申请日：2008-06-10

Applicant: IBM ,  IBM UK ,  GAUTHIER JR ROBERT ,  LI JUNJUN ,  MITRA SOUVICK ,  PUTNAM CHRISTOPHER STEPHEN ,  MOUSA MAHMOUD

Inventor： GAUTHIER JR ROBERT ,  LI JUNJUN ,  MITRA SOUVICK ,  PUTNAM CHRISTOPHER STEPHEN ,  MOUSA MAHMOUD

IPC: H01L27/02 ,  H01L21/762 ,  H01L29/74

CPC classification number: H01L27/0262

Abstract: A Silicon on Insulator (SOI) Integrated Circuit (IC) chip with devices such as a vertical Silicon Controlled Rectifier (SCR), vertical bipolar transistors, a vertical capacitor, a resistor and/or a vertical pinch resistor and method of making the device(s). The devices are formed in a seed hole through the SOI surface layer and insulator layer to the substrate. A buried diffusion, e.g., N-type, is formed through the seed hole in the substrate. A doped epitaxial layer is formed on the buried diffusion and may include multiple doped layers, e.g., a P-type layer and an N-type layer. Polysilicon, e.g., P-type, may be formed on the doped epitaxial layer. Contacts to the buried diffusion are formed in a contact liner.

Abstract translation: 具有诸如垂直硅控整流器（SCR），垂直双极晶体管，垂直电容器，电阻器和/或垂直钳位电阻器之类的器件的绝缘体上硅（SOI）集成电路（IC）芯片以及制造该器件的方法 S）。 这些器件通过SOI表面层和绝缘体层形成在种子孔中以形成衬底。 通过衬底中的种子孔形成埋入式扩散，例如N型。 掺杂的外延层形成在掩埋扩散区上，并且可以包括多个掺杂层，例如P型层和N型层。 可以在掺杂的外延层上形成例如P型的多晶硅。 到埋置扩散的接触形成在接触衬垫中。

公开(公告)号：WO2011002612A3

公开(公告)日：2011-03-10

申请号：PCT/US2010038934

申请日：2010-06-17

Applicant: IBM ,  ABOU-KHALIL MICHEL J ,  LEE TOM C ,  LI JUNJUN ,  GAUTHIER ROBERT J JR ,  PUTNAM CHRISTOPHER S ,  MITRA SOUVICK

Inventor： ABOU-KHALIL MICHEL J ,  LEE TOM C ,  LI JUNJUN ,  GAUTHIER ROBERT J JR ,  PUTNAM CHRISTOPHER S ,  MITRA SOUVICK

IPC: H01L21/82 ,  H01L27/02

CPC classification number: G11C17/16 ,  G11C11/5692 ,  H01L23/5252 ,  H01L23/5256 ,  H01L27/101 ,  H01L27/112 ,  H01L27/11206 ,  H01L45/085 ,  H01L45/1206 ,  H01L45/14 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Disclosed are embodiments of an e-fuse programming/re-programming circuit. In one embodiment, the e-fuse (150) has two short high atomic diffusion resistance conductor layers (110, 130) positioned on opposite sides (121, 122) and at a same end (123) of a long low atomic diffusion resistance conductor layer (120). A voltage source (170) is used to vary the polarity and, optionally, the magnitude of voltage applied to the terminals (first terminal = 170/161/110; second terminal = 170/162/130; third terminal = 170/163/proximate end 123 of conductor layer 120; and, fourth terminal = 170/164/distal end 124 of conductor layer 120) in order to control bi-directional flow of electrons within the long conductor layer and, thereby formation of opens and/or shorts at the long conductor layer-short conductor layer interfaces (125, 126). The formation of such opens and/or shorts can be used to achieve different programming states (11, 01, 10, 00). Other circuit structure embodiments incorporate e-fuses (650) with additional conductor layers and additional terminals so as to allow for even more programming states. Also disclosed are embodiments of associated e-fuse programming and re-programming methods.

Abstract translation: 公开了电子熔丝编程/重新编程电路的实施例。 在一个实施例中，电子熔丝（150）具有两个短的高原子扩散电阻导体层（110,130），其位于长的低原子扩散电阻导体（110,130）的相对侧（121,122）上和同一端（123） 层（120）。 使用电压源（170）来改变施加到端子（第一端= 170/161/110;第二端= 170/162/130;第三端= 170/163 / 以控制导体层120的近端123;以及导体层120的第四端子= 170/164 /远端124），以便控制长导体层内电子的双向流动，从而形成开路和/或短路 在长导体层 - 短导体层界面（125,126）处。 这种开路和/或短路的形成可以用来实现不同的编程状态（11,01,10,00）。 其他电路结构实施例将e熔丝（650）与额外的导体层和额外的端子结合，以允许更多的编程状态。 还公开了相关联的电子熔丝编程和重新编程方法的实施例。

公开(公告)号：WO2008152026A3

公开(公告)日：2009-02-19

申请号：PCT/EP2008057196

申请日：2008-06-10

Applicant: IBM ,  IBM UK ,  GAUTHIER JR ROBERT ,  LI JUNJUN ,  MITRA SOUVICK ,  PUTNAM CHRISTOPHER STEPHEN ,  MOUSA MAHMOUD

Inventor： GAUTHIER JR ROBERT ,  LI JUNJUN ,  MITRA SOUVICK ,  PUTNAM CHRISTOPHER STEPHEN ,  MOUSA MAHMOUD

IPC: H01L27/02 ,  H01L21/762 ,  H01L29/74

CPC classification number: H01L27/0262

Abstract: A Silicon on Insulator (SOI) Integrated Circuit (IC) chip with devices such as a vertical Silicon Controlled Rectifier (SCR), vertical bipolar transistors, a vertical capacitor, a resistor and/or a vertical pinch resistor and method of making the device(s). The devices are formed in a seed hole through the SOI surface layer and insulator layer to the substrate. A buried diffusion, e.g., N-type, is formed through the seed hole in the substrate. A doped epitaxial layer is formed on the buried diffusion and may include multiple doped layers, e.g., a P-type layer and an N-type layer. Polysilicon, e.g., P-type, may be formed on the doped epitaxial layer. Contacts to the buried diffusion are formed in a contact liner.

Abstract translation: 具有诸如垂直硅控制整流器（SCR），垂直双极晶体管，垂直电容器，电阻器和/或垂直钳位电阻器等器件的绝缘体硅（SOI）集成电路（IC）芯片和制造器件的方法（ S）。 器件通过SOI表面层和绝缘体层形成在晶种孔中。 通过衬底中的种子孔形成例如N型的掩埋扩散。 掺杂的外延层形成在掩埋扩散层上，并且可以包括多个掺杂层，例如P型层和N型层。 可以在掺杂的外延层上形成多晶硅，例如P型。 与埋入扩散部的接触形成在接触衬里中。

公开(公告)号：WO2008121812A1

公开(公告)日：2008-10-09

申请号：PCT/US2008/058647

申请日：2008-03-28

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  ABOU-KHALIL, Michel, J. ,  GAUTHIER, Robert ,  LI, Hongmei ,  LI, Junjun ,  MITRA, Souvick ,  PUTNAM, Christopher, S.

Inventor： ABOU-KHALIL, Michel, J. ,  GAUTHIER, Robert ,  LI, Hongmei ,  LI, Junjun ,  MITRA, Souvick ,  PUTNAM, Christopher, S.

IPC: H02H9/00

CPC classification number: H01L27/0277 ,  H01L27/0262 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An external current injection source (45A, 45B, 45D and 45E) is provided to individual fingers (40A-40E) of a multi-finger semiconductor device to provide the same trigger voltage across the multiple fingers. For example, the external injection current is supplied to the body of a MOSFET or the gate of a thyristor. The magnitude of the supplied current from each external current injection source (45 A, 45B, 45D and 45E) is adjusted so that each finger (40A-40E) has the same trigger voltage. The external current supply circuit may comprise diodes or an RC triggered MOSFET. The components of the external current supply circuit may be tuned to achieve a desired predetermined trigger voltage across all fingers of the multi-finger semiconductor device.

Abstract translation: 外部电流注入源（45A，45B，45D和45E）被提供给多指半导体器件的单个指状物（40A-40E），以在多个手指上提供相同的触发电压。 例如，外部注入电流被提供给MOSFET的主体或晶闸管的栅极。 调整来自每个外部电流注入源（45A，45B，45D和45E）的供给电流的大小，使得每个手指（40A-40E）具有相同的触发电压。 外部电流供应电路可以包括二极管或RC触发MOSFET。 可以调谐外部电流供应电路的组件以实现多指半导体器件的所有指状物上期望的预定触发电压。

公开(公告)号：WO2012047464A1

公开(公告)日：2012-04-12

申请号：PCT/US2011/051500

申请日：2011-09-14

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  ABOU-KHALIL, Michel ,  GAUTHIER, Robert, J. ,  LEE, Tom, C. ,  LI, Junjun ,  MITRA, Souvick ,  PUTNAM, Christopher, S.

Inventor： ABOU-KHALIL, Michel ,  GAUTHIER, Robert, J. ,  LEE, Tom, C. ,  LI, Junjun ,  MITRA, Souvick ,  PUTNAM, Christopher, S.

IPC: H01L27/04 ,  H01L23/60

CPC classification number: H01L27/0262 ,  H01L29/747 ,  H01L29/87 ,  H02H9/04

Abstract: Bi-directional back-to-back stacked SCRs for high-voltage pin ESD protection, methods of manufacture and design structures are provided. The device includes a symmetrical bi-directional back-to-back stacked silicon controlled rectifier (SCR). An anode (10a) of a first of the back-to-back stacked SCR (10) is connected to an input (30). An anode (20a) of a second of the back-to-back stacked SCR (20) is connected to ground (GND). Cathodes (10b, 20b) of the first and second of the back- to-back stacked SCR are connected together. Each of the symmetrical bi-directional back-to-back SCRs include a pair of diodes (Di, D2) directing current towards the cathodes which, upon application of a voltage, become reverse biased effectively deactivating elements from one of the symmetrical bi-directional back-to-back SCRs while the diodes (D3, D4) of another of the symmetrical bi-directional back-to-back SCRs direct current in the same direction as the reverse biased diodes.

Abstract translation: 提供用于高压针ESD保护的双向背对背堆叠SCR，制造方法和设计结构。 该器件包括对称双向背对背层叠可控硅整流器（SCR）。 背对背层叠SCR（10）中的第一个的阳极（10a）连接到输入（30）。 背对背层叠SCR（20）中的第二个的阳极（20a）连接到地（GND）。 第一和第二背对背层叠SCR的阴极（10b，20b）连接在一起。 对称双向背对背SCR中的每一个包括一对二极管（Di，D2），其将电流引向阴极，其在施加电压时变为反向偏置，从而有效地将激活元件从对称双向 背对背SCR，而另一个对称双向背对背SCR的二极管（D3，D4）在与反向偏置二极管相同的方向上引导电流。

公开(公告)号：WO2011002612A2

公开(公告)日：2011-01-06

申请号：PCT/US2010/038934

申请日：2010-06-17

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  ABOU-KHALIL, Michel, J. ,  LEE, Tom, C. ,  LI, Junjun ,  GAUTHIER, Robert, J., Jr. ,  PUTNAM, Christopher, S. ,  MITRA, Souvick

Inventor： ABOU-KHALIL, Michel, J. ,  LEE, Tom, C. ,  LI, Junjun ,  GAUTHIER, Robert, J., Jr. ,  PUTNAM, Christopher, S. ,  MITRA, Souvick

IPC: H01L21/82 ,  H01L27/02

CPC classification number: G11C17/16 ,  G11C11/5692 ,  H01L23/5252 ,  H01L23/5256 ,  H01L27/101 ,  H01L27/112 ,  H01L27/11206 ,  H01L45/085 ,  H01L45/1206 ,  H01L45/14 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Disclosed are embodiments of an e-fuse programming/re-programming circuit. In one embodiment, the e-fuse (150) has two short high atomic diffusion resistance conductor layers (110, 130) positioned on opposite sides (121, 122) and at a same end (123) of a long low atomic diffusion resistance conductor layer (120). A voltage source (170) is used to vary the polarity and, optionally, the magnitude of voltage applied to the terminals (first terminal = 170/161/110; second terminal = 170/162/130; third terminal = 170/163/proximate end 123 of conductor layer 120; and, fourth terminal = 170/164/distal end 124 of conductor layer 120) in order to control bi-directional flow of electrons within the long conductor layer and, thereby formation of opens and/or shorts at the long conductor layer-short conductor layer interfaces (125, 126). The formation of such opens and/or shorts can be used to achieve different programming states (11, 01, 10, 00). Other circuit structure embodiments incorporate e-fuses (650) with additional conductor layers and additional terminals so as to allow for even more programming states. Also disclosed are embodiments of associated e-fuse programming and re-programming methods.

Abstract translation: 公开了电子熔丝编程/重新编程电路的实施例。 在一个实施例中，电熔丝（150）具有位于长低原子扩散电阻导体的相对侧（121,122）和同一端（123）上的两个短的高原子扩散电阻导体层（110,130） 层（120）。 使用电压源（170）来改变极性，并且可选地改变施加到端子的电压的大小（第一端子= 170/161/110;第二端子= 170/162/130;第三端子= 170/163 / 导体层120的近端123;以及导体层120的第四端子= 170/164 /远端124），以便控制长导体层内的电子的双向流动，从而形成开口和/或短路 在长导体层 - 短导体层界面（125,126）处。 这种打开和/或短路的形成可用于实现不同的编程状态（11，01，10，00）。 其他电路结构实施例包括具有附加导体层的电子熔丝（650）和附加端子，以便允许甚至更多的编程状态。 还公开了相关联的电熔丝编程和重新编程方法的实施例。

公开(公告)号：WO2008152026A2

公开(公告)日：2008-12-18

申请号：PCT/EP2008/057196

申请日：2008-06-10

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  IBM UNITED KINGDOM LIMITED ,  GAUTHIER, JR., Robert ,  LI, Junjun ,  MITRA, Souvick ,  PUTNAM, Christopher, Stephen ,  MOUSA, Mahmoud

Inventor： GAUTHIER, JR., Robert ,  LI, Junjun ,  MITRA, Souvick ,  PUTNAM, Christopher, Stephen ,  MOUSA, Mahmoud

IPC: H01L27/02 ,  H01L29/74 ,  H01L21/762

CPC classification number: H01L27/0262

Abstract: A Silicon on Insulator (SOI) Integrated Circuit (IC) chip with devices such as a vertical Silicon Controlled Rectifier (SCR), vertical bipolar transistors, a vertical capacitor, a resistor and/or a vertical pinch resistor and method of making the device(s). The devices are formed in a seed hole through the SOI surface layer and insulator layer to the substrate. A buried diffusion, e.g., N-type, is formed through the seed hole in the substrate. A doped epitaxial layer is formed on the buried diffusion and may include multiple doped layers, e.g., a P-type layer and an N-type layer. Polysilicon, e.g., P-type, may be formed on the doped epitaxial layer. Contacts to the buried diffusion are formed in a contact liner.

Abstract translation: 具有诸如垂直硅控制整流器（SCR），垂直双极晶体管，垂直电容器，电阻器和/或垂直钳位电阻器等器件的绝缘体硅（SOI）集成电路（IC）芯片和制造器件的方法（ S）。 器件通过SOI表面层和绝缘体层形成在晶种孔中。 通过衬底中的种子孔形成例如N型的掩埋扩散。 掺杂的外延层形成在掩埋扩散层上，并且可以包括多个掺杂层，例如P型层和N型层。 可以在掺杂的外延层上形成多晶硅，例如P型。 与埋入扩散部的接触形成在接触衬里中。

公开(公告)号：US20090179267A1

公开(公告)日：2009-07-16

申请号：US12013101

申请日：2008-01-11

Applicant: Michel J. Abou-Khalil ,  Robert J. Gauthier, JR. ,  Tom C. Lee ,  Junjun Li ,  Christopher S. Putnam ,  Mitra Souvick

Inventor： Michel J. Abou-Khalil ,  Robert J. Gauthier, JR. ,  Tom C. Lee ,  Junjun Li ,  Christopher S. Putnam ,  Mitra Souvick

IPC: H01L27/12 ,  H01L21/786

CPC classification number: H01L27/1203 ,  H01L21/84

Abstract: High-voltage device structures, methods for fabricating such device structures using complementary metal-oxide-semiconductor (CMOS) processes, and design structures for high-voltage circuits. The planar device structure, which is formed using a semiconductor-on-insulator (SOI) substrate, includes a semiconductor body positioned between two gate electrodes. The gate electrodes and the semiconductor body may be formed from the monocrystalline SOI layer of the SOI substrate. A dielectric layer separates each of the gate electrodes from the semiconductor body. These dielectric layers are formed by defining trenches in the SOI layer and filling the trenches with a dielectric material, which may occur concurrent with a process forming device isolation regions.

Abstract translation: 高电压器件结构，使用互补金属氧化物半导体（CMOS）工艺制造这种器件结构的方法，以及高压电路的设计结构。 使用绝缘体上半导体（SOI）衬底形成的平面器件结构包括位于两个栅电极之间的半导体本体。 栅电极和半导体本体可以由SOI衬底的单晶SOI层形成。 电介质层将每个栅电极与半导体本体分开。 这些电介质层通过在SOI层中限定沟槽并用介电材料填充沟槽而形成，其可以与形成器件隔离区的工艺同时发生。

公开(公告)号：US07772651B2

公开(公告)日：2010-08-10

申请号：US12013101

申请日：2008-01-11

Applicant: Michel J. Abou-Khalil ,  Robert J. Gauthier, Jr. ,  Tom C. Lee ,  Junjun Li ,  Christopher S. Putnam ,  Mitra Souvick

Inventor： Michel J. Abou-Khalil ,  Robert J. Gauthier, Jr. ,  Tom C. Lee ,  Junjun Li ,  Christopher S. Putnam ,  Mitra Souvick

IPC: H01L29/78

CPC classification number: H01L27/1203 ,  H01L21/84

Abstract: High-voltage device structures, methods for fabricating such device structures using complementary metal-oxide-semiconductor (CMOS) processes, and design structures for high-voltage circuits. The planar device structure, which is formed using a semiconductor-on-insulator (SOI) substrate, includes a semiconductor body positioned between two gate electrodes. The gate electrodes and the semiconductor body may be formed from the monocrystalline SOI layer of the SOI substrate. A dielectric layer separates each of the gate electrodes from the semiconductor body. These dielectric layers are formed by defining trenches in the SOI layer and filling the trenches with a dielectric material, which may occur concurrent with a process forming device isolation regions.

Abstract translation: 高电压器件结构，使用互补金属氧化物半导体（CMOS）工艺制造这种器件结构的方法，以及高压电路的设计结构。 使用绝缘体上半导体（SOI）衬底形成的平面器件结构包括位于两个栅电极之间的半导体本体。 栅电极和半导体本体可以由SOI衬底的单晶SOI层形成。 电介质层将每个栅电极与半导体本体分开。 这些电介质层通过在SOI层中限定沟槽并用介电材料填充沟槽而形成，其可以与形成器件隔离区的工艺同时发生。