公开(公告)号：WO2006077047A1

公开(公告)日：2006-07-27

申请号：PCT/EP2006/000231

申请日：2006-01-12

Applicant: INFINEON TECHNOLOGIES AG ,  NANYA TECHNOLOGY CORPORATION ,  FEKIH-ROMDHANE, Khaled ,  LIU, Skip Shizhen

Inventor： FEKIH-ROMDHANE, Khaled ,  LIU, Skip Shizhen

IPC: G11C7/10

CPC classification number: G11C7/1051 ,  G11C7/1078

Abstract: Techniques and circuitry that support switching operations required to exchange data between memory arrays and external data pads are provided. In a write path, such switching operations may include latching in and assembling a number of bits sequentially received over a single data pad, reordering those bits based on a type of access mode (e.g., interleaved or sequential), and performing scrambling operations based on chip organization (e.g., x4, x8, or x16) a bank location being accessed. Similar operations may be performed (in reverse order) in a read path, to assemble data to be read out of a device.

Abstract translation: 提供了支持在存储器阵列和外部数据焊盘之间交换数据所需的切换操作的技术和电路。 在写入路径中，这样的切换操作可以包括锁存和组合通过单个数据焊盘顺序接收的多个位，并且基于访问模式的类型（例如，交错或顺序）重新排序这些位，并且基于 芯片组织（例如，x4，x8或x16）正在访问的银行位置。 可以在读取路径中以相反的顺序执行类似的操作，以组装要从设备读出的数据。

公开(公告)号：WO2006077046A1

公开(公告)日：2006-07-27

申请号：PCT/EP2006/000224

申请日：2006-01-12

Applicant: INFINEON TECHNOLOGIES AG ,  NANYA TECHNOLOGY CORPORATION ,  FEKIH-ROMDHANE, Khaled ,  LIU, Skip Shizhen

Inventor： FEKIH-ROMDHANE, Khaled ,  LIU, Skip Shizhen

IPC: G11C7/10

CPC classification number: G11C7/10 ,  G11C7/1018 ,  G11C7/1048 ,  G11C7/1066 ,  G11C7/1072 ,  G11C7/18

Abstract: Techniques and circuitry that support switching operations required to exchange data between memory arrays and external data pads are provided. In a write path, such switching operations may include latching in and assembling a number of bits sequentially received over a single data pad, reordering those bits based on a type of access mode (e.g., interleaved or sequential), and performing scrambling operations based on chip organization (e.g., x4, x8, or x16) a bank location being accessed. Similar operations may be performed (in reverse order) in a read path, to assemble data to be read out of a device.

Abstract translation: 提供了支持在存储器阵列和外部数据焊盘之间交换数据所需的切换操作的技术和电路。 在写入路径中，这样的切换操作可以包括锁存和组合通过单个数据焊盘顺序接收的多个位，并且基于访问模式的类型（例如，交错或顺序）重新排序这些位，并且基于 芯片组织（例如，x4，x8或x16）正在访问的银行位置。 可以在读取路径中以相反的顺序执行类似的操作，以组装要从设备读出的数据。

公开(公告)号：EP3588782A1

公开(公告)日：2020-01-01

申请号：EP18208788.2

申请日：2018-11-28

Applicant: Nanya Technology Corporation

Inventor： CHANG, Chuan-Jen ,  LEE, Wen-Ming

IPC: H03L7/00 ,  G06F1/08 ,  G06F1/16

Abstract: An operating method of a clock signal generating circuit includes the following operations: transmitting a clock signal to a clock tree circuit by a voltage detector; and adjusting a frequency of the clock signal according to a voltage of the clock tree circuit so as to maintain the voltage within a voltage range.

公开(公告)号：EP3582067A1

公开(公告)日：2019-12-18

申请号：EP18208215.6

申请日：2018-11-26

Applicant: Nanya Technology Corporation

Inventor： LEE, Wen-Ming ,  CHANG, Chuan-Jen

IPC: G06F1/324 ,  G06F1/3234 ,  G11C7/22

Abstract: A memory apparatus and a voltage control method of the memory apparatus are provided. The memory apparatus of the invention includes a synchronous circuit (102), a clock tree (104) and a memory controller (106). The synchronous circuit (102) receives a reference clock (CLKIN) and generating a clock signal (CLK). The clock tree (104) is coupled to an output end of the multiplexer (204) and assigns the clock signal (CLK) to a plurality of signal paths (108). The memory controller (106) is coupled to the synchronous circuit (102) and controls the synchronous circuit (102) to adjust a frequency of the clock signal (CLK) according to an operating mode of the memory apparatus.

公开(公告)号：EP1732125A2

公开(公告)日：2006-12-13

申请号：EP06011004.6

申请日：2006-05-29

Applicant: Nanya Technology Corporation

Inventor： Lee, Pei-Ing

IPC: H01L21/8242 ,  H01L27/108

CPC classification number: H01L27/10888 ,  H01L27/10823 ,  H01L27/10829 ,  H01L27/10876 ,  H01L27/10891 ,  H01L29/66621 ,  H01L29/7834

Abstract: A method for forming a semiconductor memory device with buried contacts. A substrate (100) is provided, wherein the substrate has recessed gates (118) and deep trench capacitor devices (102) therein. Protrusions (120) of the recessed gates and upper portions (104) of the deep trench capacitor devices are revealed. Spacers (124) are formed on sidewalls of the upper portions and the protrusions. Buried portions of conductive material (130) are formed in spaces between the spacers. The substrate, the spacers and the buried portions to form parallel shallow trenches are patterned to form parallel shallow trenches (132) for defining active regions. A layer of dielectric material is formed in the shallow trenches, wherein some of the buried portions serve as buried contacts.

Abstract translation: 一种用于与掩埋触点形成半导体存储器件的方法。 A底（100）被提供，worin衬底在其中具有凹门（118）和深沟槽电容器装置（102）。 凹入栅极与深沟槽电容器的装置的上部（104）的突起（120）显露。 间隔物（124）形成在所述上部分和所述突出的侧壁。 导电材料（130）的掩埋部分形成在间隔物之间​​的空间。 基板，间隔物和埋入部分，以形成平行的浅沟槽图案化，以形成平行的浅沟槽（132），用于活性限定区域。 电介质材料层形成在浅沟槽，worin一些埋设部16用作掩埋触点。

公开(公告)号：EP3582223A1

公开(公告)日：2019-12-18

申请号：EP18206579.7

申请日：2018-11-15

Applicant: Nanya Technology Corporation

Inventor： CHANG, Chuan-Jen ,  LEE, Wen-Ming

IPC: G11C11/406

Abstract: An operating method of a memory device includes the following operations: detecting a first temperature of the memory device; determining a first refresh rate according to the first temperature; and refreshing the memory device by the first refresh rate. The first refresh rate is lower than a refresh rate upper threshold.

公开(公告)号：EP1804288B1

公开(公告)日：2016-10-05

申请号：EP06011519.3

申请日：2006-06-02

Applicant: Nanya Technology Corporation

Inventor： Lee, Pei-Ing

IPC: H01L21/8242 ,  H01L27/108

CPC classification number: H01L27/10876 ,  H01L27/10814 ,  H01L27/10823 ,  H01L27/10829 ,  H01L27/10835 ,  H01L27/10867 ,  H01L27/10885 ,  H01L27/10891

公开(公告)号：EP1732124A2

公开(公告)日：2006-12-13

申请号：EP06010424.7

申请日：2006-05-19

Applicant: Nanya Technology Corporation

Inventor： Lee, Pei-Ing

IPC: H01L21/8242 ,  H01L27/108

CPC classification number: H01L27/10888 ,  H01L27/10823 ,  H01L27/10829 ,  H01L27/10876 ,  H01L27/10891 ,  H01L29/66621 ,  H01L29/7834

Abstract: A method for forming a semiconductor device. A substrate (100) is provided, wherein the substrate has recessed gates (118) and deep trench capacitor devices (102) therein. Protrusions (120) of the recessed gates and upper portions of the deep trench capacitor devices are revealed. Spacers (124) are formed on sidewalls of the upper portions (104) and the protrusions. Buried portions of conductive material (134a,b) are formed in spaces between the spacers. The substrate, the spacers and the buried portions are patterned to form parallel shallow trenches (132) for defining active regions. A layer of dielectric material is formed in the shallow trenches, wherein some of the buried portions (134a) serve as buried bit line contacts. Word lines (140) are formed across the recessed gates (120), wherein at least one of the word lines comprises portions overlapping the recessed gates. At least one of the overlapped portions has a narrower width than at least one of the recessed gates.

Abstract translation: 一种用于形成半导体器件的方法。 A底（100）被提供，worin衬底在其中具有凹门（118）和深沟槽电容器装置（102）。 凹入栅极与深沟槽电容器的设备的上部的突出部（120）显露。 间隔物（124）形成在所述上部分（​​104）和所述突出的侧壁。 导电材料的掩埋部分（134A，B）形成在所述间隔物之间​​的空间。 基板，间隔物和掩埋部分被图案化，以形成平行的浅沟槽（132），用于活性限定区域。 介电材料的层中的浅沟槽形成，worin一些掩埋部分（134A）作为埋位线接触。 字线（140）在各个凹陷栅极FORMED（120）worin字线中的至少一个包括重叠的凹部门。 至少重叠部分中的一个具有比所述凹门中的至少一个窄的宽度。

公开(公告)号：EP3598644A1

公开(公告)日：2020-01-22

申请号：EP18206743.9

申请日：2018-11-16

Applicant: Nanya Technology Corporation

Inventor： Chang, Chuan-Jen

IPC: H03K19/0185

Abstract: The present disclosure provides a semiconductor device. The semiconductor device includes a difference-expanding device and a receiver. The difference-expanding device receives an input signal having voltage levels representing logical states, and converts the input signal to a processed signal by changing, based on the voltage levels, degrees in conduction of the difference-expanding device. The receiver receives the processed signal from the difference-expanding device, and determines the logical states of the input signal based on the processed signal.

公开(公告)号：EP3570285A1

公开(公告)日：2019-11-20

申请号：EP18213238.1

申请日：2018-12-17

Applicant: Nanya Technology Corporation

Inventor： Chang, Chuan-Jen ,  Lee, Wen-Ming

IPC: G11C11/406 ,  G11C5/04 ,  G06F13/16

Abstract: The present disclosure provides a frequency-adjusting circuit comprising a temperature-sensing module, a computing module and a storage module. The temperature-sensing module is configured to measure temperatures of a plurality of DRAM chips. The storage module is coupled between the temperature-sensing module and the computing module, and is configured to store the temperatures of the plurality of DRAM chips. The computing module is coupled to the temperature-sensing module and is configured to compare the temperatures of the plurality of DRAM chips measured by the temperature-sensing module to determine a first temperature, to compare previous temperatures of the plurality of DRAM chips read from the storage module to determine a second temperature, and to compare the first temperature with the second temperature to determine a refresh frequency for the plurality of DRAM chips.