公开(公告)号：WO2009120546A1

公开(公告)日：2009-10-01

申请号：PCT/US2009/037453

申请日：2009-03-17

Applicant: QUALCOMM INCORPORATED ,  ROSTAMPISHEH, Ali ,  CHALLA, Raghu, N. ,  YAO, Iwen ,  SANTOS, Dave, J. ,  NATH, Mrinal, M.

Inventor： ROSTAMPISHEH, Ali ,  CHALLA, Raghu, N. ,  YAO, Iwen ,  SANTOS, Dave, J. ,  NATH, Mrinal, M.

IPC: H03M13/27

CPC classification number: H03M13/2785 ,  H03M13/2764 ,  H03M13/2771 ,  H03M13/2775 ,  H03M13/6566

Abstract: A de-interleaver generates a plurality of De-interleaved Reorder Physical (DRP) addresses to simultaneously write a corresponding plurality of LLR values into a multi-banked memory such that not more than one LLR value is written into each bank of the multi-banked memory at a time. A sequence of such parallel writes results in the LLR values of a transmission of a sub-packet being stored in the memory. Address translation performed during generation of the DRP addresses causes the LLR values to be stored within the banks such that a decoder can read LLR values out of the memory in a de-interleaved sequence. Each memory location of a bank is a word-location for storing multiple related LLR values, where one LLR value is stored along with its parity values. The ability to simultaneously write to multiple LLR values is used to clear locations in a fast and efficient manner.

Abstract translation: 解交织器生成多个解交织重排物理（DRP）地址，以将对应的多个LLR值同时写入多存储存储器，使得不多于一个LLR值被写入多存储体的每个存储体 一次记忆 这种并行写入的序列导致存储在存储器中的子包的传输的LLR值。 在生成DRP地址期间执行的地址转换导致LLR值被存储在存储体中，使得解码器可以以解交织的顺序读出存储器中的LLR值。 存储体的每个存储器位置是用于存储多个相关LLR值的字位置，其中一个LLR值与其奇偶校验值一起存储。 用于同时写入多个LLR值的能力用于以快速有效的方式清除位置。

公开(公告)号：WO2009123838A2

公开(公告)日：2009-10-08

申请号：PCT/US2009/036709

申请日：2009-03-10

Applicant: QUALCOMM INCORPORATED ,  ZANOTELLI, Joseph, V ,  NATH, Mrinal, M ,  CHAUDHURI, Arunava ,  GHOSH, Kaushik ,  CHALLA, Raghu, N. ,  JING, Weihong

Inventor： ZANOTELLI, Joseph, V ,  NATH, Mrinal, M ,  CHAUDHURI, Arunava ,  GHOSH, Kaushik ,  CHALLA, Raghu, N. ,  JING, Weihong

IPC: H04L1/00 ,  G06F9/38 ,  H03M13/29 ,  H04N7/26

CPC classification number: H04L1/0045 ,  H03M13/2957 ,  H03M13/41 ,  H03M13/6508 ,  H03M13/6561 ,  H04L1/0052

Abstract: A configurable decoder within a receiver (for example, within a wireless communication device) includes numerous decoders. In one mode, the multiple decoders are used to decode different sub-packets of a packet. When one decoder completes decoding the last sub-packet assigned to it of the packet, then that decoder generates a packet done indication. A control circuit receives the packet done indications, and when all the decoders have generated packet done indications then the control circuit initiates an action. In one example, the action is the interrupting of a processor. The processor responds by reading status information from the control circuit, thereby resetting the interrupt. End-of-packet markers are usable to generate packet done indications and to generate EOP interrupts. Similarly, end-of-group markers are usable to generate group done indications and to generate EOG interrupts. The decoder block is configurable to process sub-packets of a packet using either one or multiple decoders.

Abstract translation: 接收机内的可配置解码器（例如，在无线通信设备内）包括许多解码器。 在一种模式中，多个解码器用于解码分组的不同子分组。 当一个解码器完成对分组给它的最后一个子分组的解码时，该解码器产生分组完成指示。 控制电路接收分组完成指示，并且当所有解码器已经生成分组完成指示时，控制电路启动动作。 在一个示例中，动作是处理器的中断。 处理器通过从控制电路读取状态信息进行响应，从而复位中断。 分组结束标记可用于生成分组完成指示并产生EOP中断。 类似地，组尾标记可用于生成组完成指示并产生EOG中断。 解码器块可配置为使用一个或多个解码器来处理分组的子分组。

公开(公告)号：WO2009123838A3

公开(公告)日：2009-12-10

申请号：PCT/US2009036709

申请日：2009-03-10

Applicant: QUALCOMM INC ,  ZANOTELLI JOSEPH V ,  NATH MRINAL M ,  CHAUDHURI ARUNAVA ,  GHOSH KAUSHIK ,  CHALLA RAGHU N ,  JING WEIHONG

Inventor： ZANOTELLI JOSEPH V ,  NATH MRINAL M ,  CHAUDHURI ARUNAVA ,  GHOSH KAUSHIK ,  CHALLA RAGHU N ,  JING WEIHONG

IPC: H04L1/00 ,  G06F9/38 ,  H03M13/29 ,  H04N7/26

CPC classification number: H04L1/0045 ,  H03M13/2957 ,  H03M13/41 ,  H03M13/6508 ,  H03M13/6561 ,  H04L1/0052

Abstract: A configurable decoder within a receiver (for example, within a wireless communication device) includes numerous decoders. In one mode, the multiple decoders are used to decode different sub-packets of a packet. When one decoder completes decoding the last sub-packet assigned to it of the packet, then that decoder generates a packet done indication. A control circuit receives the packet done indications, and when all the decoders have generated packet done indications then the control circuit initiates an action. In one example, the action is the interrupting of a processor. The processor responds by reading status information from the control circuit, thereby resetting the interrupt. End-of-packet markers are usable to generate packet done indications and to generate EOP interrupts. Similarly, end-of-group markers are usable to generate group done indications and to generate EOG interrupts. The decoder block is configurable to process sub-packets of a packet using either one or multiple decoders.

Abstract translation: 接收机内的可配置解码器（例如，在无线通信设备内）包括许多解码器。 在一种模式中，多个解码器用于解码分组的不同子分组。 当一个解码器完成对分组给它的最后一个子分组的解码时，该解码器产生分组完成指示。 控制电路接收分组完成指示，并且当所有解码器已经生成分组完成指示时，控制电路启动动作。 在一个示例中，动作是处理器的中断。 处理器通过从控制电路读取状态信息进行响应，从而复位中断。 分组结束标记可用于生成分组完成指示并产生EOP中断。 类似地，组尾标记可用于生成组完成指示并产生EOG中断。 解码器块可配置为使用一个或多个解码器来处理分组的子分组。