公开(公告)号：MY147322A

公开(公告)日：2012-11-30

申请号：MYPI20055486

申请日：2005-11-24

Applicant: PHISON ELECTRONICS CORP

Inventor： WANG CHIH-LING ,  HUANG YI-HSIANG

Abstract: 28 PORTABLE STORAGE DEVICE ABSTRACT OF'114E DISCLOSURE A PORTABLE STORAGE DEVICE IS PROVIDED. THE PORTABLE STORAGE DEVICE COMPRISES A MEMORY HAVING A HIDDEN BLOCK, A FIRST PROGRAM BLOCK, A GENERAL 5 BLOCK AND A SECURITY BLOCK. A USER'S PASSWORD IS STORED IN TILE HIDDEN BLOCK AND A PASSWORD-IDENTIFYING PROGRAM IS STORED IN THE FIRST PROGRARN BLOCK. WHEN A HOST EXECUTES THE PASSWORD-IDENTIFYING PROGRAM, THE USER IS ASKED TO INPUT A PASSWORD THAT IS COMPARED WITH THE USER'S PASSWORD STORED IN TILE HIDDEN BLOCK. IF THE PASSWORD INPUTTED BY THE USER MATCHES WITH THE USER'S PASSWORD .10 STORED IN THE HIDDEN BLOCK, (LIE USER IS ALLOWED TO ACCESS TO DATA STORED IN THE SECURITY BLOCK AND TO PROCESS DATA RETRIEVAL/STORAGE THEREIN. .2 S 6@

公开(公告)号：GB0601297D0

公开(公告)日：2006-03-01

申请号：GB0601297

申请日：2006-01-24

Applicant: PHISON ELECTRONICS CORP

公开(公告)号：MY170385A

公开(公告)日：2019-07-27

申请号：MYPI2014000466

申请日：2014-02-20

Applicant: PHISON ELECTRONICS CORP

Inventor： NYUK-HOW THIAN ,  CHIH-JEN HSU

Abstract: A clock adjustment circuit (110) and a digital to analog converting device (100) are provided. The clock adjustment circuit includes a selection circuit (112) and a frequency decreasing circuit (114). The selection circuit is configured to generate a first selection signal in response to a frequency of an output clock signal. The frequency decreasing circuit is coupled to the selection circuit, and configured to generate the output clock signal by reducing a frequency of an input clock signal by a first ratio in response to a first level of the first selection signal, and configured to generate the output clock signal by reducing the frequency of the input clock signal by a second ratio in response to a second level of the first selection signal, wherein the first ratio is different from the second ratio. Accordingly, complexity of a circuit is reduced. Figure 1

公开(公告)号：MY143592A

公开(公告)日：2011-05-31

申请号：MYPI20054927

申请日：2005-10-20

Applicant: PHISON ELECTRONICS CORP

Inventor： HUANG YI-HSIANG

IPC: G11C16/06

Abstract: METHOD FOR MANAGING MEMORY BLOCKS IN FLASH MEMORY THE PRESENT INVENTION DISCLOSES A METHOD FOR MANAGING MERNORY BLOCKS 0 IN A AASH MEMORV. THE METHOD IS FIRST TO CALCULATE THE TOTAL ILUNIBER OF GOOD 1 5 BLOCKS AND TOTAL NUMBER OF BAD BLOCKS IN THE FLASH MEMORY, AND THEN ALL TILE OOOD BLOCKS AND THE BAD BLOCKS WILL BE EVENLY ALLOCATED TO EACH SEGMENT ACCORDING TO THE ILUMBER OF SEGMENTS CONTAINED IN TILE FLASH I O- . AFT R LICILL THE ALLOCATION, TILE ALLOCATION INFOR-MATION WILL BE RECORDED IN ONE GOOD BLOCK TO FORM A DATA BLOCK SO THAT WHEN THE FLASH MEMORY IS EXCCLITILLO INITIALIZATION. TILE 10 CONTROLLER CHIP MAY FIND THE DATA BLOCK, AND STORE THE DATA IN THE SRAIM (STATIC RANDOM ACCESS MEMORY) OF THE FLASH MEMORY. THEN, ACCORDING TO THE DATA STORED IN TILE SRAM, THE CONTROLLER CHIP MAY GENERATE -,I CORRESPONDING TABLE FOL- THE BLOCK CONTAINED IN THE SCURNENT ACCORDINV TO THE DATA SLORED IN THE SRAM. AS I RESULT, TILE FLASH MEMORY MAY BE USED WITH LOWER CAPACITY AND MAY 15 OBVIATE THE PROBLEM OF BEING UNUSABLE WHEN THE FLASH INERNORY CONTAINS THE EXCESSIVE AMOUNT OFTHE BAD BLOCKS. 2 0 DGOWR2@ -00/ LO X-)

公开(公告)号：MY139855A

公开(公告)日：2009-11-30

申请号：MYPI20060523

申请日：2006-02-08

Applicant: PHISON ELECTRONICS CORP

Inventor： CORP PHISON ELECTRONICS

IPC: G06F12/02

Abstract: A FLASH MEMORY AND A METHOD FOR UTILIZINO THE SAME ARE DISCLOSED. THE METHOD FOR UTILIZING A FLASH MEMORY INCLUDES THE STEPS OF: A) PROVIDING A FLASH MEMORY OF A SINGLE CHIP; B) FORMATTING THE FLASH MEMORY AND MARKING BAD BLOCKS OF THE FLASH MEMORY AS A BAD-BLOCK AREA FREE OF RELIABLE SAVED DATA; C) CALCULATING A CAPACITY OF AN AVAILABLE MEMORY WITHIN THE FLASH MEMORY, WHEREIN THE AVAILABLE MEMORY EXCLUDES THE BAD-BLOCK AREA OF THE FLASH MEMORY; AND D) DIVIDING THE AVAILABLE MEMORY INTO A FIRST STORING MEMORY AND A SECOND MEMORY, WHEREIN THE FIRST STORING MEMORY AND THE SECOND STORING MEMORY HAVE DIFFERENT CAPACITIES.

公开(公告)号：JP2012141999A

公开(公告)日：2012-07-26

申请号：JP2012032273

申请日：2012-02-17

Applicant: Phison Electronics Corp ,  群聯電子股▲ふん▼有限公司

Inventor： YU HSIANG-HSIUNG ,  SHEN YU-CHUNG ,  CHEN YUN-CHIEH

IPC: G06F21/22 ,  G06F3/06

CPC classification number: G11B20/00833 ,  G06F21/78 ,  G11B20/00086 ,  G11B20/00695 ,  G11B2020/10694 ,  G11B2020/10759 ,  G11B2020/10833 ,  G11B2020/10935 ,  G11B2020/10944 ,  G11B2220/17

Abstract: PROBLEM TO BE SOLVED: To provide a method and system for data protection, a storage device, and a storage device controller.SOLUTION: While a host accesses data stored in a storage device (410), whether the host is performing a playing process or a copying process on the data is determined (420). If it is determined that the host performs the playing process on the data, the storage device executes the playing process continually so as to allow the host to access the data (430). On the other hand, if it is determined that the host performs the copying process on the data, the storage device executes an interference procedure so as to avoid or retard the data from being copied into the host (440).

Abstract translation: 要解决的问题：提供用于数据保护的方法和系统，存储设备和存储设备控制器。 解决方案：当主机访问存储在存储设备（410）中的数据时，确定主机是否正在对数据执行播放处理或复制处理（420）。 如果确定主机对数据执行播放处理，则存储装置连续地执行播放处理，以允许主机访问数据（430）。 另一方面，如果确定主机对数据执行复制处理，则存储装置执行干扰过程以避免或阻止数据被复制到主机中（440）。 版权所有（C）2012，JPO＆INPIT

公开(公告)号：JP2007193618A

公开(公告)日：2007-08-02

申请号：JP2006011777

申请日：2006-01-19

Applicant: Phison Electronics Corp ,  群聯電子股▲ふん▼有限公司

Inventor： SHU KENKA

IPC: G06F12/16 ,  G06F12/00 ,  G06F12/02

Abstract: PROBLEM TO BE SOLVED: To provide a distributed writing method for a flash memory, extending a service life of the flash memory.
SOLUTION: A physical area of the flash memory is divided into a first area and a second area. The first area is a logical area including data and a plurality of auxiliary areas, and the second area is an area not including data, and is used for writing. When writing data, a scheduled auxiliary area is selected from the auxiliary areas of the first area, a physical block is selected from inside the other non-scheduled auxiliary areas, and a physical block is selected from the second area 2 and is set as a physical block for the writing. When a writing frequency becomes a multiple of a scheduled value, the physical block for the writing is replaced with another physical block and is set as the second area to perform writing to the physical block, the data of the physical block selected inside the first area are written in the physical block of the second area, the physical block selected from the first area is moved to the second area, and the physical block already written with the data of the second area is moved to the first area to distribute the writing frequency of each block.
COPYRIGHT: (C)2007,JPO&INPIT

Abstract translation: 要解决的问题：提供一种用于闪存的分布式写入方法，延长闪存的使用寿命。 解决方案：闪存的物理区域分为第一区域和第二区域。 第一区域是包括数据和多个辅助区域的逻辑区域，第二区域是不包括数据的区域，用于写入。 当写入数据时，从第一区域的辅助区域中选择预定的辅助区域，从其他非调度辅助区域内部选择物理块，并且从第二区域2中选择物理块，并将其设置为 物理块写作。 当写入频率变为预定值的倍数时，写入的物理块被替换为另一个物理块，并且被设置为用于对物理块执行写入的第二区域，在第一区域内选择的物理块的数据 被写入第二区域的物理块中，从第一区域选择的物理块被移动到第二区域，并且已经写入了第二区域的数据的物理块被移动到第一区域以分配写入频率 的每个块。 版权所有（C）2007，JPO＆INPIT

公开(公告)号：JP2007115103A

公开(公告)日：2007-05-10

申请号：JP2005307062

申请日：2005-10-21

Applicant: Phison Electronics Corp ,  群聯電子股▲ふん▼有限公司

Inventor： WANG CHIH-LING ,  HUANG YI-HSIANG

IPC: G06F21/24 ,  G06F3/08 ,  G06K19/073 ,  G06K19/10

Abstract: PROBLEM TO BE SOLVED: To provide a portable storage device in which data of a security protection data block is not stolen. SOLUTION: In the storage device, a connection interface connected to a host computer is installed, the connection interface connects a microcontroller to a memory, and the memory is divided into a hiding block, a first application program block, an unsecurity protection data block and a security protection data block to store an authentication program. When a user accesses data in the security protection data block, the authentication program stored in the first application program block is run, and the authentication program also compares a user ID inputted by the user with a user ID stored by the hiding block to matched with each other when the authentication program is run and subsequently sets the security protection data block as a use block, so that the user can access the data. COPYRIGHT: (C)2007,JPO&INPIT

Abstract translation: 要解决的问题：提供一种便携式存储装置，其中安全保护数据块的数据不被盗。

解决方案：在存储设备中，安装连接到主机的连接接口，连接接口将微控制器连接到存储器，并将存储器分为隐藏块，第一应用程序块，不安全保护 数据块和安全保护数据块来存储认证程序。 当用户访问安全保护数据块中的数据时，存储在第一应用程序块中的认证程序运行，并且认证程序还将由用户输入的用户ID与由隐藏块存储的用户ID进行比较，以与 彼此在运行验证程序时，并且随后将安全保护数据块设置为使用块，使得用户可以访问数据。 版权所有（C）2007，JPO＆INPIT

公开(公告)号：MY164803A

公开(公告)日：2018-01-30

申请号：MYPI20054483

申请日：2005-09-23

Applicant: PHISON ELECTRONICS CORP

Inventor： KIAN-LIANG LEE ,  WEE-KUAN GAN

IPC: G06F13/00

Abstract: A VIRTUAL UNIVERSAL SERIAL BUS (USB) FLASH MEMORY STORAGE DEVICE WITH A PERIPHERAL COMPONENT INTERCONNECT (PCI) EXPRESS INCLUDING A MICROCONTROLLER CONNECTED SEPARATELY TO A FLASH MEMORY AND PCI EXPRESS CONNECTING INTERFACE, AND THE MICROCONTROLLER HAS A FLASH MEMORY INTERFACE, A PCI EXPRESS INTERFACE AND A VIRTUAL USB MODULE AND THE VIRTUAL USB MODULE INCLUDES A USB HOST AND A USB DEVICE. IF A HOST GIVES A USB INSTRUCTION FOR SAVING OR READING TO THE STORAVE DEVICE THROUGH THE PCI EXPRESS, THE INSTRUCTION WILL BE SENT TO AND EXECUTED BY THE VIRTUAL USB MODULE AND THE REQUIRED DATA PROCESSING FOR SAVING OR READING WILL BE COMPLETED THROUGH THE FLASH MEMORY INTERFACE AND FLASH MEMORY. THE DATA IN THE STORAGE DEVICE CAN BE TRANSMITTED WITH A PCI EXPRESS STANDARD TRANSMISSION RATE, AND THE HOST CONSIDERS THE STORAGE DEVICE AS A USB DEVICE INSTEAD OF A PURE PCI EXPRESS DEVICE.

公开(公告)号：GB2434460B

公开(公告)日：2007-12-05

申请号：GB0601297

申请日：2006-01-24

Applicant: PHISON ELECTRONICS CORP

Inventor： PUA KHEIN-SENG ,  CHEN HORACE

IPC: G11C29/00 ,  G06F12/02 ,  G06F12/06