公开(公告)号：WO2005066827A2

公开(公告)日：2005-07-21

申请号：PCT/US2004043687

申请日：2004-12-23

Applicant: INTEL CORP ,  SCHMIDT DAREN J ,  PUFFER DAVID M ,  KOTAMREDDY SARATH ,  RENAUD LYONEL

Inventor： SCHMIDT DAREN J ,  PUFFER DAVID M ,  KOTAMREDDY SARATH ,  RENAUD LYONEL

IPC: G06F5/10 ,  G06F5/14 ,  G06F15/16

CPC classification number: G06F5/14

Abstract: A number of symbols are received in a first integrated circuit (IC) device, where these symbols have been transmitted by a second IC device and are received over a serial point to point link. These symbols include a non-data sequence that has been inserted into a data sequence by the second device. The symbols are loaded into a buffer. The data sequence and some of the non-data sequence is unloaded from the buffer, according to a changing unload pointer. To prevent overflow of the buffer, and in response to detecting the non-data sequence, the unload pointer is changed by more than one entry so that a non-­data symbol of the non-data sequence as loaded in the buffer is skipped while unloading from the buffer. In another embodiment, to prevent underflow of the buffer, the unload pointer is stalled at an entry of the buffer that contains a non-data symbol while unloading. Other embodiments are also described and claimed.

Abstract translation: 在第一集成电路（IC）装置中接收多个符号，其中这些符号已由第二IC器件传输并通过串行点对点链接接收。 这些符号包括已被第二设备插入到数据序列中的非数据序列。 符号被加载到缓冲区。 根据改变的卸载指针，数据序列和一些非数据序列从缓冲区中卸载。 为了防止缓冲器的溢出，并且响应于检测到非数据序列，卸载指针由多个条目改变，使得在卸载期间跳过加载在缓冲器中的非数据序列的非数据符号 从缓冲区。 在另一个实施例中，为了防止缓冲器的下溢，卸载指针在卸载期间在包含非数据符号的缓冲器的条目处被停止。 还描述和要求保护其他实施例。

公开(公告)号：WO2005066817A1

公开(公告)日：2005-07-21

申请号：PCT/US2004/043801

申请日：2004-12-23

Applicant: INTEL CORPORATION ,  RENAUD, Lyonel ,  PUFFER, David, M. ,  KOTAMREDDY, Sarath ,  MITBANDER, Suneel, G.

Inventor： RENAUD, Lyonel ,  PUFFER, David, M. ,  KOTAMREDDY, Sarath ,  MITBANDER, Suneel, G.

IPC: G06F13/38

CPC classification number: G06F13/385 ,  H04L7/042

Abstract: A stream of bits are received in a first integrated circuit (IC) device, where the stream represents a sequence of symbols transmitted by a second IC device over a serial point to point link that couples the two devices. First and second M-bit sections of the stream are compared to a non-data symbol. The second M-bit section is offset by one bit in the stream relative to the first section. If there is a match between the first section and the non-data symbol, then a flag indicating symbol alignment is asserted. Each of multiple, consecutive, non overlapping M-bit sections that follow the first section are then to be treated as separate symbols. Other embodiments are also described and claimed.

Abstract translation: 在第一集成电路（IC）设备中接收比特流，其中流表示由第二IC设备通过串联点对点链路发送的符号序列，所述串行点对点链路耦合所述两个设备。 流的第一和第二M位部分与非数据符号进行比较。 第二M位部分相对于第一部分在流中偏移一位。 如果在第一部分和非数据符号之间存在匹配，则表示符号对齐的标志被断言。 随后的第一部分之后的多个，连续的，非重叠的M位部分中的每一个然后将被视为单独的符号。 还描述和要求保护其他实施例。

公开(公告)号：WO2005066827A3

公开(公告)日：2005-07-21

申请号：PCT/US2004/043687

申请日：2004-12-23

Applicant: INTEL CORPORATION ,  SCHMIDT, Daren, J. ,  PUFFER, David, M. ,  KOTAMREDDY, Sarath ,  RENAUD, Lyonel

Inventor： SCHMIDT, Daren, J. ,  PUFFER, David, M. ,  KOTAMREDDY, Sarath ,  RENAUD, Lyonel

IPC: G06F5/06

Abstract: A number of symbols are received in a first integrated circuit (IC) device, where these symbols have been transmitted by a second IC device and are received over a serial point to point link. These symbols include a non-data sequence that has been inserted into a data sequence by the second device. The symbols are loaded into a buffer. The data sequence and some of the non-data sequence is unloaded from the buffer, according to a changing unload pointer. To prevent overflow of the buffer, and in response to detecting the non-data sequence, the unload pointer is changed by more than one entry so that a non-­data symbol of the non-data sequence as loaded in the buffer is skipped while unloading from the buffer. In another embodiment, to prevent underflow of the buffer, the unload pointer is stalled at an entry of the buffer that contains a non-data symbol while unloading. Other embodiments are also described and claimed.

公开(公告)号：WO2005066816A1

公开(公告)日：2005-07-21

申请号：PCT/US2004/043526

申请日：2004-12-22

Applicant: INTEL CORPORATION ,  RENAUD, Lyonel ,  PUFFER, David, M. ,  KOTAMREDDY, Sarath ,  SCHMIDT, Daren, J. ,  MITBANDER, Suneel, G.

Inventor： RENAUD, Lyonel ,  PUFFER, David, M. ,  KOTAMREDDY, Sarath ,  SCHMIDT, Daren, J. ,  MITBANDER, Suneel, G.

IPC: G06F13/38

CPC classification number: H04L25/14 ,  G06F13/385 ,  H04L49/90

Abstract: Multiple symbol sequences that have been transmitted in parallel using the same transmit clock over a serial point to point link are received. Each symbol sequence includes an instance of a first, non-data symbol. The multiple symbol sequences are buffered and the number of times an instance of a second, non-data symbol that occurs in one of the symbol sequences is changed. A first deskew process is performed, followed by a second deskew process. The first deskew process aligns an instance of the first non-data symbol in every one of the buffered symbol sequences. The second deskew process equalizes the number of instances of the second non-data symbol that follow an instance of the first non-data symbol in every one of the symbol sequences. Other embodiments are also described and claimed.

Abstract translation: 接收到通过串行点对点链路使用相同传输时钟并行发送的多个符号序列。 每个符号序列包括第一非数据符号的实例。 缓冲多个符号序列，并且发生在符号序列之一中的第二非数据符号的实例的次数被改变。 执行第一个偏移过程，然后进行第二个偏移处理。 第一个偏移校正过程对齐每个缓冲符号序列中的第一个非数据符号的一个实例。 第二个偏移校正过程使每个符号序列中的第一非数据符号的实例之后的第二非数据符号的实例的数量相等。 还描述和要求保护其他实施例。

公开(公告)号：WO2005066765A3

公开(公告)日：2005-07-21

申请号：PCT/US2004/043418

申请日：2004-12-23

Applicant: INTEL CORPORATION ,  PUFFER, David, M. ,  MITBANDER, Suneel, G. ,  KOTAMREDDY, Sarath, K.

Inventor： PUFFER, David, M. ,  MITBANDER, Suneel, G. ,  KOTAMREDDY, Sarath, K.

IPC: G06F1/32

Abstract: A transmitting device and a receiving device are coupled together via an interconnect. An electrical idle ordered set is received at the receiving device power management unit after having been transmitted by the transmitting device and received at the input pins of the receiving device and moving through the receiver logic pipeline. At the time the electrical idle ordered set has been recognized at the end of the receiver logic pipeline, the power management unit checks for activity on the interconnect.. If there is no activity on the interconnect, then the power management unit causes the receiving device to enter a low power state where the receiver circuitry (input buffers) is turned off. If there is activity on the interconnect when the electrical idle ordered set is received at the power management unit, then the power management unit does not cause the receiver circuitry to be tuned off.

公开(公告)号：WO2005066765A2

公开(公告)日：2005-07-21

申请号：PCT/US2004043418

申请日：2004-12-23

Applicant: INTEL CORP ,  PUFFER DAVID M ,  MITBANDER SUNEEL G ,  KOTAMREDDY SARATH K

Inventor： PUFFER DAVID M ,  MITBANDER SUNEEL G ,  KOTAMREDDY SARATH K

IPC: G06F1/32 ,  G06F9/00

CPC classification number: G06F1/3253 ,  G06F1/3203 ,  Y02D10/151

Abstract: A transmitting device and a receiving device are coupled together via an interconnect. An electrical idle ordered set is received at the receiving device power management unit after having been transmitted by the transmitting device and received at the input pins of the receiving device and moving through the receiver logic pipeline. At the time the electrical idle ordered set has been recognized at the end of the receiver logic pipeline, the power management unit checks for activity on the interconnect.. If there is no activity on the interconnect, then the power management unit causes the receiving device to enter a low power state where the receiver circuitry (input buffers) is turned off. If there is activity on the interconnect when the electrical idle ordered set is received at the power management unit, then the power management unit does not cause the receiver circuitry to be tuned off.

Abstract translation: 发射设备和接收设备经由互连耦合在一起。 在接收设备功率管理单元已经由发送设备发送并且在接收设备的输入引脚处接收并且通过接收机逻辑流水线移动之后，接收电空闲有序集合。 当在接收器逻辑流水线的末端已经识别到电空闲有序集时，电源管理单元检查互连上的活动。如果互连上没有活动，则电源管理单元使接收设备 进入接收器电路（输入缓冲器）关闭的低功率状态。 如果在电源管理单元接收到电空闲命令集时互连上有活动，则电源管理单元不会使接收器电路关闭。