-
公开(公告)号：WO2013105913A4
公开(公告)日：2013-11-14
申请号：PCT/US2011062501
申请日：2011-11-30
Applicant: INTEL CORP , RAMADOSS MURALI , SAMSON ERIC
Inventor： RAMADOSS MURALI , SAMSON ERIC
CPC classification number: G09G5/18 , G06F1/324 , G06F1/3265 , G06F3/14 , G06T1/20 , G06T1/60 , G09G2330/021 , G09G2340/0435 , Y02D10/126 , Y02D10/153 , Y02D50/20
Abstract: Examples are disclosed for adjusting a performance state of a graphics subsystem and/or a processor based on a comparison of an average frame rate to a target frame rate and also based on whether the graphics subsystem is in a burst mode or sustained mode of operation.
Abstract translation: 公开了用于基于平均帧速率与目标帧速率的比较并且还基于图形子系统是处于突发模式还是持续运行模式来调整图形子系统和/或处理器的性能状态的示例。
-
公开(公告)号：WO2020190426A1
公开(公告)日：2020-09-24
申请号：PCT/US2020/017747
申请日：2020-02-11
Applicant: INTEL CORPORATION , COORAY, Niran , SADLER, William B. , PEARCE, Jonathan D. , PETRE, Marian Alin , ASHBAUGH, Ben , RAMADOSS, Murali , VEMULAPALLI, Vikranth , SHAH, Ankur N. , SANKARAN, Rajesh
Inventor： COORAY, Niran , SADLER, William B. , PEARCE, Jonathan D. , PETRE, Marian Alin , ASHBAUGH, Ben , RAMADOSS, Murali , VEMULAPALLI, Vikranth , SHAH, Ankur N. , SANKARAN, Rajesh
Abstract: Methods and apparatus relating to transactional page fault handling. In an example, an apparatus comprises a processor to divide an execution thread of a graphics workload into a set of transactions which are to be executed atomically, initiate the execution of the thread, and manage the execution of the thread according to one of a first protocol in response to a determination that a page fault occurred in the execution of a transaction, or a second protocol in response to a determination that a page fault did not occur in the execution of a transaction. Other embodiments are also disclosed and claimed.
-
公开(公告)号：WO2014014628A1
公开(公告)日：2014-01-23
申请号：PCT/US2013/047638
申请日：2013-06-25
Applicant: INTEL CORPORATION , VEMBU, Balaji , NAVALE, Aditya , RAMADOSS, Murali , STANDRING, David, I. , BALA, Kritika
Inventor： VEMBU, Balaji , NAVALE, Aditya , RAMADOSS, Murali , STANDRING, David, I. , BALA, Kritika
IPC: G06F9/46
CPC classification number: G06F9/4881 , Y02D10/24
Abstract: A computing device for performing scheduling operations for graphics hardware is described herein. The computing device includes a central processing unit (CPU) that is configured to execute an application. The computing device also includes a graphics scheduler configured to operate independently of the CPU. The graphics scheduler is configured to receive work queues relating to workloads from the application that are to execute on the CPU and perform scheduling operations for any of a number of graphics engines based on the work queues.
Abstract translation: 本文描述了用于执行图形硬件的调度操作的计算设备。 计算设备包括被配置为执行应用的中央处理单元（CPU）。 计算设备还包括被配置为独立于CPU操作的图形调度器。 图形调度器被配置为接收与在CPU上执行的应用程序的工作负载有关的工作队列，并且基于工作队列对多个图形引擎中的任何一个执行调度操作。
-
公开(公告)号：WO2020190431A1
公开(公告)日：2020-09-24
申请号：PCT/US2020/017995
申请日：2020-02-12
Applicant: INTEL CORPORATION , ASHBAUGH, Ben , PEARCE, Jonathan , RAMADOSS, Murali , VEMULAPALLI, Vikranth , SADLER, William B. , KIM, Sungye , PETRE, Marian Alin
Inventor： ASHBAUGH, Ben , PEARCE, Jonathan , RAMADOSS, Murali , VEMULAPALLI, Vikranth , SADLER, William B. , KIM, Sungye , PETRE, Marian Alin
Abstract: Embodiments are generally directed to thread group scheduling for graphics processing. An embodiment of an apparatus includes a plurality of processors including a plurality of graphics processors to process data; a memory; and one or more caches for storage of data for the plurality of graphics processors, wherein the one or more processors are to schedule a plurality of groups of threads for processing by the plurality of graphics processors, the scheduling of the plurality of groups of threads including the plurality of processors to apply a bias for scheduling the plurality of groups of threads according to a cache locality for the one or more caches.
-
公开(公告)号：WO2020190425A1
公开(公告)日：2020-09-24
申请号：PCT/US2020/017743
申请日：2020-02-11
Applicant: INTEL CORPORATION , RAY, Joydeep , ANANTARAMAN, Aravindh , APPU, Abhishek R. , KOKER, Altug , OULD-AHMED-VALL, ElMoustapha , ANDREI, Valentin , MAIYURAN, Subramaniam , GALOPPO VON BORRIES, Nicolas , MACPHERSON, Mike , ASHBAUGH, Ben , RAMADOSS, Murali , VEMULAPALLI, Vikranth , SADLER, William , PEARCE, Jonathan , KIM, Sungye , GEORGE, Varghese
Inventor： RAY, Joydeep , ANANTARAMAN, Aravindh , APPU, Abhishek R. , KOKER, Altug , OULD-AHMED-VALL, ElMoustapha , ANDREI, Valentin , MAIYURAN, Subramaniam , GALOPPO VON BORRIES, Nicolas , MACPHERSON, Mike , ASHBAUGH, Ben , RAMADOSS, Murali , VEMULAPALLI, Vikranth , SADLER, William , PEARCE, Jonathan , KIM, Sungye , GEORGE, Varghese
Abstract: Methods and apparatus relating to scalar core integration in a graphics processor. In an example, an apparatus comprises a processor to receive a set of workload instructions for a graphics workload from a host complex, determine a first subset of operations in the set of operations that is suitable for execution by a scalar processor complex of the graphics processing device and a second subset of operations in the set of operations that is suitable for execution by a vector processor complex of the graphics processing device, assign the first subset of operations to the scalar processor complex for execution to generate a first set of outputs, assign the second subset of operations to the vector processor complex for execution to generate a second set of outputs. Other embodiments are also disclosed and claimed.
-
Patent Agency Ranking
公开(公告)号：WO2015199971A1
公开(公告)日：2015-12-30
申请号：PCT/US2015/034890
申请日：2015-06-09
Applicant: INTEL CORPORATION , RAMADOSS, Murali , PENDLURU, Nishanth R. , FRIZZELL, Jeffrey S. , SHAH, Ankur N.
Inventor： RAMADOSS, Murali , PENDLURU, Nishanth R. , FRIZZELL, Jeffrey S. , SHAH, Ankur N.
CPC classification number: G06T1/20 , G06F9/5044 , G06F2209/509 , Y02D10/22
Abstract: Methods and systems may provide for receiving, at a controller, a notification of a workload submission by an application lacking system level privileges. Additionally, the controller may be used to schedule a transfer of the workload submission to a graphics hardware component for execution, wherein the controller has system level privileges. In one example, the transfer bypasses an operating system and a kernel mode driver associated with the graphics hardware component.
Abstract translation: 方法和系统可以规定在控制器处由缺少系统级特权的应用程序接收工作负载提交的通知。 此外，控制器可以用于调度将工作负载提交传送到图形硬件组件以供执行，其中控制器具有系统级特权。 在一个示例中，转移绕过与图形硬件组件相关联的操作系统和内核模式驱动器。
-
公开(公告)号：WO2013101155A1
公开(公告)日：2013-07-04
申请号：PCT/US2011/068032
申请日：2011-12-30
Applicant: INTEL CORPORATION , KOKER, Altug , NAVALE, Aditya , VEMBU, Balaji , RAMADOSS, Murali
Inventor： KOKER, Altug , NAVALE, Aditya , VEMBU, Balaji , RAMADOSS, Murali
CPC classification number: G06F9/50 , G06F9/4812 , G06F9/545 , G06F12/1491 , G06F15/167
Abstract: Transitions to ring 0, each time an application wants to use an adjunct processor, are avoided, saving central processor operating cycles and improving efficiency. Instead, initially each application is registered and setup to use adjunct processor resources in ring 3.
Abstract translation: 每次应用程序想要使用辅助处理器时，转换到0，避免中断处理器运行周期并提高效率。 相反，最初每个应用程序都被注册并设置为在环3中使用辅助处理器资源。
-
公开(公告)号：WO2020190429A1
公开(公告)日：2020-09-24
申请号：PCT/US2020/017897
申请日：2020-02-12
Applicant: INTEL CORPORATION , VEMULAPALLI, Vikranth , STRIRAMASSARMA, Lakshminarayanan , MACPHERSON, Mike , ANANTARAMAN, Aravindh , ASHBAUGH, Ben , RAMADOSS, Murali , SADLER, William B. , PEARCE, Jonathan , JANUS, Scott , INSKO, Brent , RANGANATHAN, Vasanth , SINHA, Kamal , HUNTER, Arthur , SURTI, Prasoonkumar , GALOPPO VON BORRIES, Nicolas , RAY, Joydeep , APPU, Abhisek R. , OULD-AHMED-VALL, ElMoustapha , KOKER, Altug , KIM, Sungye , MAIYURAN, Subramaniam , ANDREI, Valentin
Inventor： VEMULAPALLI, Vikranth , STRIRAMASSARMA, Lakshminarayanan , MACPHERSON, Mike , ANANTARAMAN, Aravindh , ASHBAUGH, Ben , RAMADOSS, Murali , SADLER, William B. , PEARCE, Jonathan , JANUS, Scott , INSKO, Brent , RANGANATHAN, Vasanth , SINHA, Kamal , HUNTER, Arthur , SURTI, Prasoonkumar , GALOPPO VON BORRIES, Nicolas , RAY, Joydeep , APPU, Abhisek R. , OULD-AHMED-VALL, ElMoustapha , KOKER, Altug , KIM, Sungye , MAIYURAN, Subramaniam , ANDREI, Valentin
IPC: G06F12/0862 , G06F12/0897 , G06F12/0888 , G06F9/38
Abstract: Embodiments are generally directed to data prefetching for graphics data processing. An embodiment of an apparatus includes one or more processors including one or more graphics processing units (GPUs); and a plurality of caches to provide storage for the one or more GPUs, the plurality of caches including at least an L1 cache and an L3 cache, wherein the apparatus to provide intelligent prefetching of data by a prefetcher of a first GPU of the one or more GPUs including measuring a hit rate for the L1 cache; upon determining that the hit rate for the L1 cache is equal to or greater than a threshold value, limiting a prefetch of data to storage in the L3 cache, and upon determining that the hit rate for the L1 cache is less than a threshold value, allowing the prefetch of data to the L1 cache.
-
公开(公告)号：WO2020190422A1
公开(公告)日：2020-09-24
申请号：PCT/US2020/017521
申请日：2020-02-10
Applicant: INTEL CORPORATION , RAMADOSS, Murali , VEMULAPALLI, Vikranth , COORAY, Niran , SADLER, William B. , PEARCE, Jonathan D. , PETRE, Marian Alin , ASHBAUGH, Ben , OULD-AHMED-VALL, ElMoustapha , GALOPPO VON BORRIES, Nicolas , KOKER, Altug , ANANTARAMAN, Aravindh , MAIYURAN, Subramaniam , GEORGE, Varghese , KIM, Sungye , VALENTIN, Andrei
Inventor： RAMADOSS, Murali , VEMULAPALLI, Vikranth , COORAY, Niran , SADLER, William B. , PEARCE, Jonathan D. , PETRE, Marian Alin , ASHBAUGH, Ben , OULD-AHMED-VALL, ElMoustapha , GALOPPO VON BORRIES, Nicolas , KOKER, Altug , ANANTARAMAN, Aravindh , MAIYURAN, Subramaniam , GEORGE, Varghese , KIM, Sungye , VALENTIN, Andrei
Abstract: Methods and apparatus relating to predictive page fault handling. In an example, an apparatus comprises a processor to receive a virtual address that triggered a page fault for a compute process, check a virtual memory space for a virtual memory allocation for the compute process that triggered the page fault and manage the page fault according to one of a first protocol in response to a determination that the virtual address that triggered the page fault is a last page in the virtual memory allocation for the compute process, or a second protocol in response to a determination that the virtual address that triggered the page fault is not a last page in the virtual memory allocation for the compute process. Other embodiments are also disclosed and claimed.
-
公开(公告)号：WO2013105913A3
公开(公告)日：2013-09-26
申请号：PCT/US2011062501
申请日：2011-11-30
Applicant: INTEL CORP , RAMADOSS MURALI , SAMSON ERIC
Inventor： RAMADOSS MURALI , SAMSON ERIC
CPC classification number: G09G5/18 , G06F1/324 , G06F1/3265 , G06F3/14 , G06T1/20 , G06T1/60 , G09G2330/021 , G09G2340/0435 , Y02D10/126 , Y02D10/153 , Y02D50/20
Abstract: Examples are disclosed for adjusting a performance state of a graphics subsystem and/or a processor based on a comparison of an average frame rate to a target frame rate and also based on whether the graphics subsystem is in a burst mode or sustained mode of operation.
Abstract translation: 公开了用于基于平均帧速率与目标帧速率的比较以及还基于图形子系统处于突发模式还是持续操作模式来调整图形子系统和/或处理器的性能状态的示例。
-
-
-
-
-
-
-
-
-
Search Results
14
records
(took 0.018 seconds)
