Abstract:
A method for performing power routing on a voltage island within an integrated circuit chip is disclosed. A first power grid (31) is generated for a voltage island on metal levels 1 to N-1. Then a second power grid is generated on metal levels N and above (32). A bounding region of the second robust power grid is determined (33). Finally, the shortest distance connections from a set of power sources is routed to the second power grid (34).
Abstract:
A method for performing power routing on a voltage island within an integrated circuit chip is disclosed. A first power grid (31) is generated for a voltage island on metal levels 1 to N-1. Then a second power grid is generated on metal levels N and above (32). A bounding region of the second robust power grid is determined (33). Finally, the shortest distance connections from a set of power sources is routed to the second power grid (34).